Dual port RAM

Details Dual port RAM Dual port RAM

2006-06-20

2006-06-20

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S025000

Reexamination Certificate

active

07065686

ABSTRACT:
A dual port RAM includes an any-time readable/writable memory block in which an access can be made to the same storage area from independent first and second ports. In addition, the RAM includes a first test circuit for performing a test to the storage area of the memory block via the first port on the basis of a first clock signal, and a second test circuit for performing a test to the storage area of the memory block via the second port on the basis of a second clock signal. A control circuit of the RAM causes the first and second test circuits to test the memory block in an alternating manner.

REFERENCES:
patent: 6104663 (2000-08-01), Kablanian
patent: 6269036 (2001-07-01), Shubat
patent: 2003/0120974 (2003-06-01), Adams et al.
Wang et al., “A Built-In Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters”, Nov. 19-21, 2001, 10th Asian IEEE Test Symposium 2001, pp. 103-108.
Wu et al., “Shadow Write and Read for At-Speed BIST of TDM SRAMs”, Oct. 30-Nov. 1, 2001, IEEE International Test Conference 2001, pp. 985-994.

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