Dual port memory word size expansion technique

Details Dual port memory word size expansion technique Dual port memory word size expansion technique

1985-02-04

1986-12-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 700

Patent

active

046270302

ABSTRACT:
An improved technique for word size expansion using dual port random access memories (DPRs) allows multiple integrated circuit chips to be used without introducing erroneous data. A master chip provides a signal derived from its conflict resolution circuitry to one or more slave chips. This prevents one or more chips in a word size expansion arrangement from selecting opposite ports when two access requests arrive simultaneously. An optional address latch input to the chips allows the retention of the same address hold time parameter for the expanded word as for a single DPR chip.

REFERENCES:
patent: 4016541 (1977-04-01), Delagi et al.
patent: 4028675 (1977-06-01), Frankenberg
patent: 4380798 (1983-04-01), Shannon et al.
"SY2130/SY2131 1024.times.8 Dual Port Random Access Memory", Synerteck, Mar., 1984, pp. 1-12.
"MCM68HC34 Dual-Port RAM Memory Unit", Motorola Semiconductors Products, Inc., 1984, pp. 1-9.
"Asynchronous Dual-Port RAM Simplifies Multiprocessor Systems", EDN, K. W. Pope, Sep. 1, 1983, pp. 147-154.
"WCM7804PX-24 Dual Port RAM", AT&T Preliminary Data Sheet, Mar. 1984, pp. 1-12.
"Memory Components-512.times.9 Biport.TM. Parallel In-Out FIFO MK4501/MK68345 N-12, 15, 20", United Technologies Mostek, 1983, pp. 1-12.

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