Dual port memory device with reduced coupling effect

Details Dual port memory device with reduced coupling effect Dual port memory device with reduced coupling effect

2006-07-18

2009-08-18

Jackson, Jr., Jerome (Department: 2815)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C257SE27098, C257S369000

Reexamination Certificate

active

07577040

ABSTRACT:
A dual port SRAM cell includes at least one pair of cross-coupled inverters connected between a power line and complementary power line. A number of pass gate transistors connect the cross-coupled inverters to a first bit line, a first complementary bit line, a second bit line, and a second complementary bit line on a first metal layer in the memory device. A first word line is coupled to gates of the first and second pass gate transistors, located on a second metal layer in the memory device. A second word line is coupled to gates of the third and fourth pass gate transistors, located on a third metal layer in the memory device, wherein the first, second and third metal layers are at different levels.

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Chinese Office Action 2007100846852.

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