Dual port memory device and a method therefor

Details Dual port memory device and a method therefor Dual port memory device and a method therefor

1996-02-08

1998-10-20

Nelms, David C.

Static information storage and retrieval

Addressing

Multiple port access

365221, 36523009, G11C 800

Patent

active

058257136

ABSTRACT:
A dual port memory device and method for outputting serial data at a high speed from a memory array through a data register. The device includes a RAM port and a SAM port. The SAM port receives start column address data from the RAM port during a transfer cycle and the data register is filled with row data from a specified row. During this process, the start column address is latched and incremented, then the incremented address loaded into a serial counter as an initial address to set up a pipeline serial output. After completion of the transfer cycle, the serial counter is controlled by a serial clock and causes column data to be prefetched from the data register and supplied to an output buffer for serial output. Because of the pipeline configuration, data is serially output at a high speed.

REFERENCES:
patent: 5042014 (1991-08-01), Pinkham et al.
patent: 5287324 (1994-02-01), Nagashima
patent: 5379263 (1995-01-01), Ogawa et al.
patent: 5475649 (1995-12-01), Balistreri et al.
patent: 5617368 (1997-04-01), Ishida
patent: 5661692 (1997-08-01), Pinkham et al.

Affiliated with

Also associated with

Rating

Dual port memory device and a method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual port memory device and a method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual port memory device and a method therefor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-252781