Dual port memory controller

Details Dual port memory controller Dual port memory controller

1987-10-20

1989-01-03

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

364900, 365219, 365222, 365230, G11C 1300

Patent

active

047962321

ABSTRACT:
A dual port memory controller is operative to interface a pair of processors to a common multiple bank organized memory. A dedicated logic array provides arbitration between conflicting processor requests for memory access. Refresh means are operative upon the memory banks in a staggered fashion to minimize noise created within the system during refresh and to permit simultaneous refresh of an access to the memory.

REFERENCES:
patent: 4683555 (1987-07-01), Pinkham

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