Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1985-01-14
1987-04-21
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365154, 365203, G11C 1300
Patent
active
046601775
ABSTRACT:
A dual port memory is implemented in complementary (e.g., CMOS) technology so as to allow simultaneous uncontested read operations to the same memory cell. This is achieved by accessing one node of a bistable static cell through a n-channel and a p-channel access transistor. The opposite node is typically left unconnected to external access means. This technique also reduces the area required to implement the memory cell as compared to prior art NMOS techniques. If desired, an arbitration circuit can be included to arbitrate between simultaneous read/read or read/write operations on the same cell from the two ports.
REFERENCES:
patent: 4447891 (1984-05-01), Kadota
patent: 4541076 (1985-09-01), Bowers et al.
"Dual-Port 8k RAM Allows 2-.mu.P Memory Access", EDN, B. Travis, Aug. 1983, p. 100.
"Asynchronous Dual-Port RAM Simplifies Multiprocessor Systems", EDN, K. W. Pope, Sep. 1983, pp. 147-154.
"Smart Memories Seek Honors in Proliferating Small Systems", Electronics, R. Beresford, Jul. 1982, pp. 89-98.
"High-Density, Buried-Contact CMOS/SOS Static RAM's", International Electron Devices Meeting, A. G. F. Dingwall et al., 1978, pp. 193-196.
"16K CMOS/SOS Asynchronous Static RAM", IEEE International Solid-State Circuits Conference, A. G. F. Dingwall et al., Feb. 1979, pp. 104-105, 286.
American Telephone and Telegraph Company
AT&T Bell Laboratories
Fears Terrell W.
Fox James H.
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