Dual port cell structure

Static information storage and retrieval – Addressing – Multiple port access

Reexamination Certificate

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C365S154000, C365S063000

Reexamination Certificate

active

07405994

ABSTRACT:
Disclosed are improved layouts for memory cell and memory cell arrays. A memory cell array of multiple memory cells connected by signal lines that twist in connecting the array. Further, an eight transistor memory cell that comprises different resistive paths as seen by the signal lines electrically connected to the cell and asymmetric pass devices associated with those resistive paths. Furthermore, an eight transistor memory cell that includes butt contacts.

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