Dual mode logic circuit for a memory array

Details Dual mode logic circuit for a memory array Dual mode logic circuit for a memory array

1984-05-18

1986-08-26

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365179, 365242, 307455, 307467, G11C 700, H03K 19086

Patent

active

046086676

ABSTRACT:
An electronically selectable high performance data path switch which allows one input to drive two data buses or to have two inputs drive the two independently.

REFERENCES:
patent: 3333113 (1967-07-01), Cole
patent: 3446989 (1969-05-01), Allen
patent: 3539824 (1970-11-01), Yu et al.
patent: 3681614 (1972-08-01), Kroos
patent: 3789243 (1974-01-01), Donofrio
patent: 3906212 (1975-09-01), Poguntke
patent: 3925691 (1975-12-01), Gaskill
patent: 3942033 (1976-03-01), Swiatowiec
patent: 4007384 (1977-02-01), Brooks
patent: 4066915 (1978-01-01), Ohhinata
patent: 4070657 (1978-01-01), Fett
patent: 4099070 (1978-05-01), Reinert
patent: 4110639 (1978-08-01), Redwine
patent: 4125877 (1978-11-01), Reinert
patent: 4149099 (1979-04-01), Nagami
patent: 4215418 (1980-05-01), Muramatsu
patent: 4274017 (1981-06-01), Carter
patent: 4280070 (1981-07-01), Reese
patent: 4540900 (1985-09-01), Early et al.
Cooperman, "High Speed Current Mode Logic for LSI", IEEE Tranactions on Circuits and Systems, vol. CAS 127, No. 7, Jul. 1980, pp. 626-635.
Skokan, "Emitter Function Logic-Logic Family for LSI", IEEE Journal of Solid State Circuits, vol. SL-8, No. 5, Oct. 1973, pp. 356-361.
Gascoigne, "Logic Circuit Can Realise Any Boolean Function of Three Variables", Electronic Engineering, vol. 42, No. 513, Nov. 1970, pp. 69-72.
Hurst, "Universal Logic Gates in Custom-Designed I.C. Applications", International Conference on Computer Aided Design and Manufacture of Electronic Components, Circuits and Systems (Brighton, England), Jul. 3-6, 1979, pp. 61-65.
"Cascode Current Switch, Latched Input", IBM Technical Disclosure Bulletin, vol, 21, No. 6, Nov. 1978 by R. D. Burke, p. 2406.
"Low Power Write Circuit for Fast VLSI Arrays" by R. D. Dussault et al, IBM Technical Disclosure Bulletin, vol. 24, No. 11A, Apr. 1982, p. 5630.

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