Dual metal gate finFETs with single or dual high-K gate...

Details Dual metal gate finFETs with single or dual high-K gate... Dual metal gate finFETs with single or dual high-K gate...

2007-09-25

2010-02-09

Tran, Long K (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S157000, C438S213000, C438S283000, C438S313000, C438S322000, C438S592000, C257SE21242, C257SE21630, C257SE21631, C257SE21632, C257SE21703

Reexamination Certificate

active

07659157

ABSTRACT:
A first high-k gate dielectric layer and a first metal gate layer are formed on first and second semiconductor fins. A first metal gate ring is formed on the first semiconductor fin. In one embodiment, the first high-k gate dielectric layer remains on the second semiconductor fin. A second metal gate layer and a silicon containing layer are deposited and patterned to form gate electrodes. In another embodiment, a second high-k dielectric layer replaces the first high-k dielectric layer over the second semiconductor fin, followed by formation of a second metal gate layer. A first electrode comprising a first gate dielectric and a first metal gate is formed on the first semiconductor fin, while a second electrode comprising a second gate dielectric and a second metal gate is formed on the second semiconductor fin. Absence of high-k gate dielectric materials on a gate wiring prevents increase in parasitic resistance.

REFERENCES:
patent: 2007/0128858 (2007-06-01), Haukka et al.
patent: 2009/0065870 (2009-03-01), Li et al.

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