Dual metal gate CMOS devices and method for making the same

Details Dual metal gate CMOS devices and method for making the same Dual metal gate CMOS devices and method for making the same

2001-03-27

2003-06-03

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S229000, C438S299000

Reexamination Certificate

active

06573134

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to MOS transistors and IC fabrication method, and specifically to a dual metal gate CMOS device and the fabrication thereof.
BACKGROUND OF THE INVENTION
Dual metal gate CMOS devices are suggested in the 1999 edition of
International Technology Roadmap for Semiconductors,
however, that publication neither teaches nor suggests any process for making such devices, nor does it specify materials or parameters for making dual metal gate CMOS devices.
Current CMOS devices use polysilicon as the gate electrode for both the NMOS and the PMOS transistor, wherein N+ polysilicon is used for the NMOS transistor, while P+ polysilicon is used for the PMOS. Because of gate depletion problems associated with polysilicon, replacing the polysilicon with metal is expected to provide a more reliable and efficient CMOS device.
There are currently two techniques for placement of metal electrodes in IC devices: one is to use a metal electrode with the Fermi level at the middle of the Si band gap. The second technique is to use dual metal: one metal functions similarly to that of N+ polysilicon in the NMOS transistor, and a second, different metal functions similarly to P+ polysilicon in the PMOS transistor.
SUMMARY OF THE INVENTION
A method of fabricating a dual metal gate CMOS, includes preparing a silicon substrate to form device areas, wherein each device area includes an n-well and a p-well; forming a gate oxide in a gate region and depositing a place-holder gate in each of the n-well and p-well; implanting ions to form a source region and a drain region in each of the n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure.
A dual metal gate CMOS of the invention includes a substrate having an n-well to form a PMOS transistor and a p-well to form a NMOS transistor, each having a gate region, a source region and a drain region; in the NMOS, a gate including a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup; in the PMOS, a gate including a high-k cup and a second metal gate formed in the high-k cup; wherein the first metal is taken from the group of metals consisting of platinum and iridium; and wherein the second metal is taken from the group of metals consisting of aluminum, zirconium, molybdenum, niobium, thallium, thallium nitride and vanadium.
It is an object of the invention to provide an efficient, reliable dual metal gate CMOS device.
Another object of the invention is to provide a CMOS device wherein polysilicon is not used in the gate region.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.


REFERENCES:
patent: 6291282 (2001-09-01), Wilk et al.
patent: 6303418 (2001-10-01), Cha et al.
patent: 6365450 (2002-04-01), Kim
patent: 6406956 (2002-06-01), Tsai et al.
patent: 6410376 (2002-06-01), Ng et al.
patent: 6444512 (2002-09-01), Madhukar et al.

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