Dual metal CMOS transistors with silicon-metal-silicon...

Details Dual metal CMOS transistors with silicon-metal-silicon... Dual metal CMOS transistors with silicon-metal-silicon...

2006-03-28

2006-03-28

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S592000

Reexamination Certificate

active

07018887

ABSTRACT:
A method of forming dual metal CMOS transistors includes forming a first silicon layer on a gate dielectric layer provided on a substrate. A first metal layer is formed on the NMOS device areas. A second metal layer is formed on the PMOS device areas. These first and second metal layers consist of different metals. A second silicon layer is deposited on the first and second metal layers. A dry etching technique is performed to etch the second silicon layer, the first and second metal layers, and the first silicon layer. The dry etching stops on the gate dielectric layer, thereby forming gate electrodes. The first and second metal layers are reacted with the first and second silicon layers to form suicides in the gate electrodes.

REFERENCES:
patent: 6027961 (2000-02-01), Maiti et al.
patent: 6503788 (2003-01-01), Yamamoto
patent: 6881631 (2005-04-01), Saito et al.
patent: 2003/0216038 (2003-11-01), Madhukar et al.

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