Dual mask process for semiconductor devices

Details Dual mask process for semiconductor devices Dual mask process for semiconductor devices

2001-01-17

2002-08-06

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000

Reexamination Certificate

active

06429067

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the manufacture of integrated circuit devices on a semiconductor substrate. In particular, the present invention relates to a fabrication process for making a logic device with embedded memory where the memory and logic FETs require only one additional DUV mask to create separate hard masks for the gate in DRAM arrays, DRAM support, and logic devices.
BACKGROUND OF THE INVENTION
With the advent of Large Scale Integration (LSI), many integrated circuit designs include several circuit functions on a single semiconductor substrate. Modem semiconductor devices usually require different circuit functions on a single chip, such as memory storage and logic functions for addressing and accessing the memory. The semiconductor industry continually is striving to enhance device performance, while still maintaining, or preferably reducing, manufacturing costs of these devices. An approach taken by the industry to accomplish both reduced cost and increased performance has been the integration of logic devices and memory devices on the same semiconductor substrate. Logic circuit and a DRAM cell region formed on the same substrate define an embedded DRAM. The integration of memory and logic improves performance by decreasing communication delays between memory devices on one chip and logic devices located on a second chip. In addition, processing costs for integrating memory and logic devices on the same semiconductor substrate potentially could be reduced due to the sharing of specific processing steps used to fabricate both types of devices.
SUMMARY OF THE INVENTION
The fabrication of embedded DRAM in planar MOSFET cells has involved employing a bordered contact etch process for the DRAM array area of the substrate. This can be attributed to the lack of a cap nitride layer for the a borderless contact etch procedure. Accordingly, reduction in cell size in the array area of e-DRAM has been precluded from approaching the cell size of stand alone DRAM with comparable minimum ground rules for fabrication. However, according to the present invention, by utilizing a dual hard mask approach including a first mask (such as a tetraethoxysilane (TEOS) layer) of a material resistant to a first etch but removable by a second etch, and a second mask (such as a silicon nitride layer) over the first mask, of a material that is resistant to a second etch but removable by a first etch, only one additional DUV photolithographic mask is required to create separate hard masks for gate structures in DRAM arrays, DRAM support, and logic devices. The nitride layer on top of a polysilicon layer over the gate oxide areas in the arrays serves as an etch stop for the subsequent self-aligned contact etch process, thus enabling further cell size reduction in the array area of the embedded DRAM. By patterning gate structure on array devices and logic devices using a nitride/TEOS bilayer hard mask on the array devices and a TEOS layer hard mask on the logic devices allows the formation of borderless contacts in the array area while maintaining tight control of the polysilicon gate dimensions in the logic area.


REFERENCES:
patent: 6037222 (2000-03-01), Huang et al.
patent: 6287907 (2001-09-01), Ito et al.
patent: 6291279 (2001-09-01), Hsiao et al.

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