Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-03-09
2003-03-18
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S622000, C438S624000, C438S633000, C438S637000, C438S638000
Reexamination Certificate
active
06534389
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to silicon device manufacturing and in particular to an improved method for forming contact wiring to substrate devices.
2. Related Art
Silicon devices are continually being made smaller with the goals of increasing both device speed and circuit density. The miniaturized devices built within and upon a semiconductor substrate are spaced very closely together and their package density continues to increase significantly. As the package density increases, silicon devices are subject to electrical and physical limitations which stem from their reduced size.
One type of silicon device experiencing such electrical limitations is the array of storage cells on a static random access memory (SPAM) chip. Individual SRAM storage cells typically consist of a single metal oxide semiconductor field effect transistor (MOSFET) and a single capacitor. These cells are used throughout the electronic industry for storing a single bit of data as an electrical signal.
In metal oxide semiconductor (MOS) devices, polysilicon film has been the form of metallization used for gates and also for connecting to MOS devices. The inability of further miniaturization of the contact metallization and the first level connections (i.e., MOS on the substrate) is a major obstacle in the miniaturization of SRAMs and other devices, such as MOS and bipolar devices. Typically, cell capacitors are formed with a sidewall spacer surrounding a portion of a polysilicon layer. As cell density increases, the thickness of this sidewall spacer and other features is necessarily decreased, creating an obstacle to increasing circuit density in SRAMs. In particular, pulldown at the top of the sidewall spacer causes electrical shorting of the diffusion contact to the gate during salicidation, rendering the device inoperable. Thus, the problems encountered when forming smaller first level contacts and first level interconnections, and the problems of decreased feature size must be resolved to enable further increases in circuit density in semiconductor devices.
Utilization of self-aligned contacts is useful in semiconductor fabrication because they reduce the difficulties associated with precise alignment, thus allowing a considerable shrinkage in device size. Borderless contacts are contacts that are placed on the contact mounting surfaces of the substrate, and which may overlap adjacent features within the device, for example, sidewall spacers and gate conductors, without producing an electrical short circuit. The utilization of borderless contacts provides several advantages in semiconductor device manufacturing. First, borderless contacts enable production of a device having contact mounting surfaces that are smaller than the contacts placed upon them. Second, borderless contacts allow for compensation of manufacturing tolerances. Finally, the risk of electrical short circuits between device elements is eliminated.
Many of the related art methods require substantially more processing steps and/or planar structures which make the manufacturing process more complex and costly. Also, other processing methods rely on etching to a predetermined etch depth which can be quite difficult to control in a manufacturing environment. Therefore, it is desirable to develop processes that are as simple as possible to implement, and also provide methods that do not require etches without distinct stopping layers.
SUMMARY OF THE INVENTION
The present invention is directed to a method of forming diffusion and gate contacts, by forming a borderless diffusion contact adjacent to a first capped gate electrode followed by forming contacts to the borderless contact and to a second non-capped gate electrode.
The invention is further directed to a method of forming a contact structure on a semiconductor substrate having a plurality of electronic elements thereon, including capped gate electrodes and uncapped gate electrodes of field effect transistors, the contact structure establishing an electrical connection between selected ones of said electronic elements and an interconnecting conductive layer, comprising the steps of:
forming a lower planarized insulator structure on the substrate;
forming a plurality of borderless conductive vias in said lower planarized insulator structure, said borderless vias partially overlaying the capped gate electrodes;
forming an upper planarized insulator structure on said lower planarized insulator structure; and
forming an upper planarized insulator structure on said lower planarized insulator structure; and
forming a second plurality of conductive vias in said upper planarized insulator structure, at least some of said second plurality of conductive vias contacting said borderless vias, and at least some others of said second plurality of conductive vias comprising bordered vias to the uncapped gate electrodes on the substrate.
The invention is further directed to a contact structure on a semiconductor substrate having a plurality of electronic elements thereon, including capped gate electrodes and uncapped gate electrodes of field effect transistors, the contact structure establishing an electrical connection between selected ones of said electronic elements and an interconnecting conductive layer, comprising:
a lower planarized insulator structure on the substrate;
a plurality of borderless conductive vias in said lower planarized insulator structure, said borderless vias partially overlaying the capped gate electrodes;
an upper planarized insulator structure on said lower planarized insulator structure; and
a second plurality of conductive vias in said upper planarized insulator structure, at least some of said second plurality of conductive vias contacting said borderless vias, and at least some others of said second plurality of conductive vias comprising bordered vias to the uncapped gate electrodes on the substrate.
It is a further advantage to provide a semiconductor device having substantially coplanar contact mounting surfaces, comprising:
a substrate having at least one diffusion region and at least one gate stack;
three distinct stacked insulative layers, namely inner, middle, and outer, deposited upon the substrate;
contacts formed within the three insulative layers which provide connection to the diffusion region;
contacts formed within the three insulative layers which provide connection to the gate stack; and
wherein the contacts within the middle insulative layer have a cross-sectional area smaller than that of the contacts within the outer insulative layer.
The foregoing and other objects, features and advantages of the invention will be apparent in the following and more particular description of the preferred embodiments of the invention as illustrated in the accompanying drawings.
REFERENCES:
patent: 4851361 (1989-07-01), Schumann et al.
patent: 5115296 (1992-05-01), Hsue et al.
patent: 5362666 (1994-11-01), Dennison
patent: 5401691 (1995-03-01), Caldwell
patent: 5466636 (1995-11-01), Cronin et al.
patent: 5554557 (1996-09-01), Koh
patent: 5578524 (1996-11-01), Fukase et al.
patent: 5677557 (1997-10-01), Wuu et al.
patent: 5710073 (1998-01-01), Jeng et al.
patent: 5718800 (1998-02-01), Juengling
patent: 5792703 (1998-08-01), Bronner et al.
patent: 5817562 (1998-10-01), Chang et al.
patent: 5831899 (1998-11-01), Wang et al.
patent: 5849622 (1998-12-01), Hause et al.
patent: 5858837 (1999-01-01), Sakoh et al.
patent: 5895948 (1999-04-01), Mori et al.
patent: 5895961 (1999-04-01), Chen
patent: 5899722 (1999-05-01), Huang
patent: 5899742 (1999-05-01), Sun
patent: 5907781 (1999-05-01), Chen et al.
patent: 6004853 (1999-12-01), Yang et al.
patent: 6074912 (2000-06-01), Lin et al.
patent: 6121129 (2000-09-01), Greco et al.
patent: 6159844 (2000-12-01), Bothra
patent: 6174803 (2001-01-01), Harvey
patent: 6223432 (2001-05-01), Dennison et al.
patent: 6287951 (2001-09-01), Lucas et al.
patent: 6291335 (2001-09-01), Schnabel et al.
patent: 6319813 (2001-11-01), Givens
Ference Thomas G.
Kimmel Kurt R.
Loiseau Alain
Rankin Jed H.
Jr. Carl Whitehead
Sabo William D.
Schmeiser Olsen & Watts
Thomas Toniae M.
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