Dual layer silicide formation using a titanium barrier to...

Details Dual layer silicide formation using a titanium barrier to... Dual layer silicide formation using a titanium barrier to...

2001-07-11

2002-12-17

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S630000, C438S649000, C438S656000

Reexamination Certificate

active

06495460

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices and methods for their manufacture. In particular, the present invention relates to formation of silicide on semiconductor devices with decreased roughness between a doped silicon region and a metal silicide region.
DESCRIPTION OF THE RELATED ART
One of the major goals of integrated circuit design is to produce ever smaller integrated circuits without forfeiting performance. For instance, in designing metal oxide silicon (MOS) stransistors, manufacturing smaller components implies the need to design transistors with shorter gates. When the size of a MOS gate is decreased, it is necessary to decrease the size of the source and drain regions in order to reduce leakage current. However, this reduction in size of source and drain regions creates further problems, as electrical connections between the doped silicon of the source and drain regions and metal interconnects have high characteristic resitivity. Higher source/drain (S/D) resistivity results in slower operation of the semiconductor device. The gains obtained by producing semiconductor devices with reduced dimensions are offset by the decrease in device speed caused by increased source/drain resistivity.
One approach to addressing the problem of high source/drain resistivity is through self-aligned silicide (salicide) technology. Metal silicides have the advantage of having reduced resistivities as compared to doped-silicon alone. In general, this approach entails layering a metal such as nickel directly over the source and drain regions of a MOS device. An annealing process causes the metal to diffuse into the doped-silicon region of the device, where a metal silicide is formed. In the case of nickel, a nickel silicide (NiSi) is the metal silicide that is formed. This silicide layer segregates over the doped silicon S/D region. Unreacted metal is then stripped from the device, for instance with a 4:1 mixture of sulfuric acid (H
2
SO
4
) and hydrogen peroxide (H
2
O
2
), leaving a metal silicide layer over the source/drain regions. The silicide layer presents a much lower interface resistivity with respect to metal interconnects than does the doped silicon source or drain region. For example, TiSi
2
has a resistivity of 15-20 &mgr;&OHgr;cm, CoSi
2
has a resistivity of 17-20 &mgr;&OHgr;cm, and NiSi has a resistivity of 12-15 &mgr;&OHgr;cm.
A typical prior art method of manufacturing a semiconductor device using silicide technology may be envisioned with reference to
FIGS. 1-4
. A typical prior art semiconductor device
10
is depicted in FIG.
1
. Semiconductor device
10
is a metal oxide semiconductor (MOS) device comprising a silicon substrate
12
, a doped silicon source region
14
a
, a doped silicon drain region
14
b
, a gate dielectric
18
and a gate electrode
16
. Typically, source region
14
a
and drain region
14
b
will be doped with the same dopant material, such as As, P, or B, depending on whether the substrate
12
is crystalline silicon, p-doped silicon or n-doped silicon. Semiconductor device
10
also has spacers
180
that provide electrical isolation between the source/drain regions
14
a
,
14
b
and the gate electrode
16
. The spacers
180
comprise an insulative material, such as silicon nitride (SiN), silicon dioxide (SiO
2
) or silicon oxynitride (SiON). The spacers
180
are added after source/drain extensions are implanted, and prior to implantation and activation of dopant, such as As, to form the source/drain regions
14
a
,
14
b
. The spacers
180
shield the source/drain extensions from further doping during the doping of the source/drain regions
14
a
,
14
b.
As discussed above, a semiconductor device such as MOS device
10
will tend to exhibit relatively high resistivity at source
14
a
and drain
14
b
. A typical prior art method of overcoming this problem is through application of silicide technology. A first step of a prior art process employing silicide technology is depicted in
FIG. 2. A
metal layer
106
, such as nickel (Ni), is applied to the surface of silicon substrate
12
, source
14
a
, drain
14
b
, gate dielectric
18
and gate electrode
16
. The device
10
is then subjected to one or more rapid thermal annealing (RTA) steps. After or between the RTA step(s), the unreacted metal layer is removed.
FIG. 3
depicts device
10
after the RTA and unreacted metal removal steps. Source
14
a
is overlaid with a metal silicide layer
104
a
, while drain
14
b
is overlaid with a corresponding metal silicide layer
104
b
. Gate
16
also has a metal silicide layer
116
formed at its top surface. The metal silicide layers
104
a
,
104
b
,
116
provide reduced resistivity to connects (not shown) that will be applied to the metal silicide layers
104
a
,
104
b
,
116
of device
10
in later fabrication steps.
However, silicide technology is not without its drawbacks. Among these drawbacks is the tendency of certain silicide layers to form a rough interface between the doped portion of the source/drain regions and their corresponding silicide layers. This has been particularly noted with respect to nickel silicides when used in conjunction with As-doped source/drain regions.
FIG. 4
depicts a zoom view of part of a typical prior art device
10
employing silicide technology. The device
10
comprises silicon substrate
12
, metal gate dielectric
18
, gate electrode
16
, doped silicon region
14
and silicide layers
104
,
116
. The interface between doped silicon region
14
and silicide layer
104
is a rough border
106
. Such surface roughness results in greater than optimal resistivity and capacitive reactance, both of which negatively impact device speed. It is therefore desirable to form a smoother border between doped silicon regions and overlying metal silicide layers.
SUMMARY OF THE INVENTION
There is a need for a semiconductor device having a smooth border between doped source/drain regions and overlying metal silicide layers, and a method of forming such a semiconductor device when the silicide includes nickel, and the dopant is arsenic.
This and other needs are met by embodiment of the present invention, which provide a method of fabricating a semiconductor device having a silicide junction having a smooth border between a doped silicon region and a mixed metal silicide region, the method comprising providing a silicon substrate having a doped silicon region disposed thereon, applying a layer of titanium metal over at least the doped silicon region, applying a layer of nickel over at least the titanium layer, subjecting the silicon substrate, doped-silicon region, titanium layer and nickel layer to rapid thermal annealing, and removing the titanium and nickel layers to produce a semiconductor device having a silicide junction having a smooth border between a doped silicon region and a silicide region thereof.
The earlier stated needs are also met by embodiments of the present invention, which provide an integrated circuit device having a silicide junction, having a smooth border between a doped silicon region and a silicide region, comprising: a doped silicon region; a silicide region overlying the doped silicon region, the silicide and doped silicon regions forming a silicide junction having a smooth border between the silicide and doped silicon regions; wherein the silicide region comprises silicon, nickel and titanium atoms.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5814537 (1998-09-01), Maa et al.
patent: 5994747 (1999-11-01), Wu
patent: 5998248 (1999-12-01), Ma et al.
patent: 6093628 (2000-07-01), Lim et al.
patent: 6303504 (2001-10-01), Lin
Setton et al. “Formation of ternary silicide for Ni/Ti/Si (100) and Ni/TiSi2” Journal of Materials Research 4(5), Sep./Oct. 1989, pp. 1218-1226.*
Horache et al. “Ti/Ni bilayers on silicon: sputter-induced intermixing, rapid thermal ann

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