Dual layer polysilicon capacitor node DRAM process

Details Dual layer polysilicon capacitor node DRAM process Dual layer polysilicon capacitor node DRAM process

1993-04-19

1998-11-24

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438252, 438394, H01L 218242

Patent

active

058406050

ABSTRACT:
A gate silicon oxide layer is formed on the silicon substrate. A doped layer of polysilicon is formed over the gate silicon oxide layer. The polysilicon layer is patterned to provide the gate electrodes of the transistor. Source/drain regions are formed through ion implantation followed by spacer formation. A node contact oxide is blanket deposited and an opening is formed therein to the silicon substrate at the location of the buried contact. A dual layer of polysilicon is deposited over the node contact oxide and within the opening to the substrate. This dual layer consists of a bottom layer of undoped polysilicon and a top layer of in-situ doped polysilicon wherein the relative thicknesses of the two layers have been determined to optimize both concentration of dopant at the surface of the capacitor node and junction depth. The substrate is annealed to drive in the buried junction. The dual polysilicon layers are patterned to form the capacitor node. A capacitor dielectric is deposited followed by an in-situ doped polysilicon layer which will form the top capacitor plate. An insulating layer is blanket deposited. An opening is made in the insulating layer to the capacitor plate at the boundary of the cell layer. The contact is completed by the deposition and patterning of a metal layer to complete construction of the capacitor, gate electrode, and source/drain structures with buried contacts.

REFERENCES:
patent: 5021357 (1991-06-01), Taguchi et al.
patent: 5100825 (1992-03-01), Fazan et al.
patent: 5110752 (1992-05-01), Lu
patent: 5118640 (1992-06-01), Fujii et al.

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