Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
2001-08-07
2003-02-11
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S258000
Reexamination Certificate
active
06518151
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of integrated circuit devices. The invention particularly relates to integrating, on a single chip of “embedded Dynamic Access Memory” (eDRAM) products, self-aligned, borderless contacts in DRAM arrays in a first region and bordered contacts in a logic support area in a second region, using a single poly-Si patterning process (lithography and etch) and a single contact definition process. The invention addresses the problem of fabrication of an integrated circuit chip having two different layout rules on the same chip. In this case, a highly packed layout is used for the gate contacts of the DRAM array region in contrast to a more separated layout for gate contacts in the region containing support logic circuits. Components are concurrently fabricated in both areas, overcoming prior art techniques of having to deal separately with the respective region devices.
2. Description of the Related Art
In a prior filing application Ser. No. 09/765,036, filed on Jan. 17, 2001), a method was described of using two separate critical DUV photoresist masks to form the dual gates sequentially with a blocking non-critical MUV photoresist mask for separation. However, this method has a higher manufacturing cost due to the use of two DUV masks. In another prior art re-oxidized polysilicon gate inside the contact holes provides the isolation instead of using thick cap nitride layer. The drawback of this scheme is that it has very narrow process windows and is difficult for manufacturing.
In the closed packed DRAM array, there is no room for contact borders, so the borderless contacts are preferred which in turn requires the use of a thick nitride cap layer to protect the polysilicon gate when the contact via etch is being made in between the closely packed gate lines. On the other hand, the logic area has no such requirement and the need for a silicidation process precludes the use of thick cap nitride layer. This invention aims to provide a novel scheme to create such a structure having two distinctive layout requirements.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for generating self-aligned, borderless contacts in DRAM arrays and bordered contacts in a logic support area on eDRAM products using a single contact definition process (lithography and etch).
It is an additional object of the invention to provide a fabrication method for a chip containing regions having different design rule requirements.
It is an additional object to provide a method that is simpler, less costly, and relaxes the litho overlay requirement for the MOL (middle of the line) process.
To achieve the above objects and goals, according to a first aspect of the invention, described herein is a method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule, including: using a first material to establish a first hard mask pattern in only the first region; and, using a second material to establish a second hard mask pattern on top of the first hard mask pattern, the second material further establishing a third hard mask pattern in the second region.
According to a second aspect of the invention, described herein is a method of fabricating eDRAM on an integrated circuit chip, including: using a first material to establish a first hard mask pattern only in a first region to contain a DRAM array; and, using a second material to establish a second hard mask pattern on top of the first hard mask pattern, the second material further establishing a third hard mask pattern in a second region.
According to a third aspect of the invention, described herein is a method of fabricating eDRAM on an integrated circuit chip, including: initially depositing an oxide layer over the top surface of the chip, using a first material to establish a first hard mask pattern only in a first region of the chip, where the first region is preselected to include a DRAM array; using a second material to establish a second hard mask pattern on top of the first hard mask pattern, where the second material further establishes a third hard mask pattern in a second region of the chip, where the second region is preselected to contain control logic; using an etch process to form gate stacks simultaneously in the first region and the second region; and, forming simultaneously borderless contact studs in the first region and bordered contact studs in the second region.
According to a fourth aspect of the invention, described herein is a method of fabricating eDRAM on an integrated circuit chip, including: using a first material to establish a first hard mask pattern only in a first region of the chip, where the first region is preselected to include a DRAM array; using a second material to establish a second hard mask pattern on top of the first hard mask pattern, where the second material additionally is used to establish a third hard mask pattern in a second region of the chip, where the second region is preselected to include control logic; and forming simultaneously borderless contact studs in the first region and bordered contact studs in the second region.
According to a fifth aspect of the invention, described herein is a method of fabricating an integrated circuit chip having a first region having a first set of devices with a first layout rule and a second region having a second set of devices with a second layout rule, the method including: forming a dual hard mask in the first region; and, simultaneously forming the first set of devices and the second set of devices.
REFERENCES:
patent: 5886410 (1999-03-01), Chiang et al.
patent: 6037222 (2000-03-01), Huang
patent: 6069037 (2000-05-01), Liao
patent: 6117730 (2000-09-01), Komori et al.
patent: 6153459 (2000-11-01), Sun
Dobuzinsky David Mark
Khan Babar Ali
Liu Joyce C.
Wensley Paul R.
Yu Chienfan
Blecker Ira D.
Dang Phuc T.
International Business Machines - Corporation
McGinn & Gibb PLLC
LandOfFree
Dual layer hard mask for eDRAM gate etch process does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual layer hard mask for eDRAM gate etch process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual layer hard mask for eDRAM gate etch process will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3143636