Dual gate structure, fabrication method for the same,...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE21637

Reexamination Certificate

active

07635897

ABSTRACT:
In one embodiment, a semiconductor device includes at least two stacked gate structures formed on a substrate. The two stacked gate structures each include a semiconductor layer and a metal layer over the semiconductor layer. The two stacked gate structures on the substrate are characterized by differential intermediate layers, one of the two structures including an ohmic layer and the other of the two structures not including an ohmic layer.

REFERENCES:
patent: 6165858 (2000-12-01), Gardner et al.
patent: 6743704 (2004-06-01), Takahashi
patent: 2001/0030342 (2001-10-01), Ohnishi et al.
patent: 2002/0004263 (2002-01-01), Tanabe et al.
patent: 2002/0102796 (2002-08-01), Lee et al.
patent: 2005/0073011 (2005-04-01), Taguwa
Fumio Ohtake, Yasushi Akasaka, et al. A Thin Amorphous Silicon Buffer Process for Suppression of W Polymetal Gate Depletion in PMOS'IEEE 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 74-75.

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