Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2006-04-18
2006-04-18
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S704000, C438S745000, C438S751000
Reexamination Certificate
active
07030024
ABSTRACT:
A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.
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Chen Chi-Chun
Chen Chih-Chang
Ho Tuo-Hung
Wang Ming-Fang
Yang Chih-Wei
Duane Morris LLP
Norton Nadine G.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tran Binh X.
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