Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-08-23
2000-03-07
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438218, 438219, H01L 218238
Patent
active
060339438
ABSTRACT:
A semiconductor manufacturing process for producing MOS integrated circuits having two gate oxide thickness is provided. A first gate dielectric is formed on an upper surface of a semiconductor substrate. Thereafter, a masking layer is deposited on the first dielectric layer and patterned such that the first dielectric layer is exposed above a second region of the semiconductor substrate. The semiconductor wafer is then subjected to a thermal oxidation process such that a second gate dielectric is formed within the exposed second region of the semiconductor substrate. The second gate dielectric preferably has an oxide thickness that is unequal to the oxide thickness of the first gate dielectric layer. Thereafter, gate structures and source/drain structures are fabricated such that the integrated circuit includes a first transistor having a first gate dielectric thickness and a second transistor having a second gate dielectric thickness. In this manner, the integrated circuit can include selected transistors having a thinner gate dielectric for improving the performance of these selected transistors. In one embodiment, the n-channel transistors in a CMOS integrated circuit have a thinner gate oxide than the p-channel devices.
REFERENCES:
patent: 4098618 (1978-07-01), Crowder et al.
patent: 4352117 (1982-09-01), Cuomo et al.
patent: 4551910 (1985-11-01), Patterson
patent: 4578128 (1986-03-01), Mundt et al.
patent: 4682407 (1987-07-01), Wilson et al.
patent: 4707721 (1987-11-01), Ang et al.
patent: 4729009 (1988-03-01), Ang
patent: 4743566 (1988-05-01), Bastiaens et al.
patent: 4774197 (1988-09-01), Haddad et al.
patent: 4776925 (1988-10-01), Fossum et al.
patent: 4808261 (1989-02-01), Ghidini et al.
patent: 4851257 (1989-07-01), Young et al.
patent: 4866002 (1989-09-01), Shizukuishi et al.
patent: 4897365 (1990-01-01), Baldi et al.
patent: 4922319 (1990-05-01), Fukushima
patent: 5043780 (1991-08-01), Fazan et al.
patent: 5066995 (1991-11-01), Young et al.
patent: 5082797 (1992-01-01), Chan et al.
patent: 5102832 (1992-04-01), Tuttle
patent: 5138411 (1992-08-01), Sandhu
patent: 5141882 (1992-08-01), Komori et al.
patent: 5158463 (1992-10-01), Kim et al.
patent: 5172200 (1992-12-01), Muragishi et al.
patent: 5191509 (1993-03-01), Wen
patent: 5208176 (1993-05-01), Ahmad et al.
patent: 5250456 (1993-10-01), Bryant
patent: 5254489 (1993-10-01), Nakata
patent: 5296411 (1994-03-01), Gardner et al.
patent: 5308787 (1994-05-01), Hong et al.
patent: 5316965 (1994-05-01), Philipossian et al.
patent: 5316981 (1994-05-01), Gardner et al.
patent: 5330920 (1994-07-01), Soleimani et al.
patent: 5330935 (1994-07-01), Dobuzinsky et al.
patent: 5340764 (1994-08-01), Larsen et al.
patent: 5358894 (1994-10-01), Fazan et al.
patent: 5362685 (1994-11-01), Gardner et al.
patent: 5387540 (1995-02-01), Poon et al.
patent: 5391907 (1995-02-01), Jang
patent: 5432114 (1995-07-01), O
patent: 5480828 (1996-01-01), Hsu et al.
patent: 5498577 (1996-03-01), Fulford, Jr. et al.
patent: 5502009 (1996-03-01), Lin
patent: 5576226 (1996-11-01), Hwang
patent: 5576266 (1996-11-01), Flosenzier et al.
patent: 5576570 (1996-11-01), Ohsawa et al.
patent: 5591681 (1997-01-01), Wristers et al.
patent: 5604159 (1997-02-01), Cooper et al.
patent: 5637520 (1997-06-01), Cappelletti et al.
patent: 5672521 (1997-09-01), Barsan et al.
patent: 5683925 (1997-11-01), Irani et al.
patent: 5786256 (1998-07-01), Gardner et al.
patent: 5789305 (1998-08-01), Peidous
patent: 5851893 (1998-12-01), Gardner et al.
patent: 5861347 (1999-01-01), Maiti et al.
patent: 5872376 (1999-02-01), Gardner et al.
patent: 5882993 (1999-03-01), Gardner et al.
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, p.p. 429-446, No Month Given 1986.
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 3: The Submicron MOSFET, Sunset Beach, CA, p.p. 429-446, No Month Given 1995.
Yoshikawa et al., "An EPROM Cell Structure for EPLD's Compatible with Single Poly-Si Gate Process," IEEE Transactions on Electron Devices, vol. 37, No. 3, Mar. 1990, pp. 675-679.
Wolfe, S., "Silicon Processing For The VLSI Era," vol. 3, The Submicron Mosfet, Lattice Press, CA, 1995, pp. 495-496.
International Search Report for International Application No. PCT/US 97/09424 mailed Sep. 16, 1997.
Patent Abstracts of Japan, Publication No. 01183844; Publication Date: Jul. 21, 1989; Application Date: Jan. 19, 1988; Application No. 63008901.
Kuroi, et al "Novel NICE Structure For High Reliability and High Performance 0.25 micron Dual Gate CMOS", IEDM, pgs. 325-328. No month/y.
Molle, P. et al., "Nitrogen Implantation for Local Oxidation of Silicon," Nuclear Instruments & Methods in Physics Research, Section--B: Beam Interactions with Materials and Atoms, vol. B55, No. 1 / 04, Apr. 2, 1991, pp. 860-865.
Schott, K. et al., "Blocking of Silicon Oxidation by Low-Dose Nitrogen Implantation," Applied Physics A. Solids and Surfaces, vol. A45, No. 1, Jan. 1, 1988, pp. 73-76.
Doyle, B. et al., "Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing," IEEE Electron Device Letters, vol. 16, No. 7, Jul. 1995, pp. 301-302.
Ahn, J. et al., "High Quality Ultrathin Gate Dieletrics Formation by Thermal Oxidation of Si in N20," J. Electrochem. Soc. V. 139, No. 9, Sep. 1991, pp. L39-41.
Philipossian, A. et al., "Kinetics of Oxide Growth During Reoxidation of Lightly Nitrided Oxides," J. Electrochem. Soc. V. 139, No. 9, Sep. 1992, pp. L82-3.
Wolf, "Silicon Processing For the VLSI Era", vol. 1, Process Technology, pp. 198-218. 1986 No Month.
Naito et al., "Effect of Bottom Oxide on the Integrity of Interpolysilicon Ultrathin ONO Films," Journal of the Electrochemical Society, vol. 137, No. 2, Feb. 1, 1990, pp. 635-638.
Abbas et al., "Improvement of the Gate-Region Integrity in FET Devices," IBM Technical Disclosure Bulletin, vol. 14, No. 11, Apr. 1972, pp. 3348-3350.
Cheung, "Plasma Immersion Ion Implantation for ULSI Processing," Trends & Applications, 1991, pp. 811-820.
Wolf et al., "Silicon Processing for the VLSI Era, vol. 1, Process Technology," p. 321.
Advanced Micro Devices , Inc.
Daffer Kelvin L.
Lattin Christopher
Niebling John F.
LandOfFree
Dual gate oxide thickness integrated circuit and process for mak does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual gate oxide thickness integrated circuit and process for mak, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual gate oxide thickness integrated circuit and process for mak will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-362315