Dual gate oxide formation with minimal channel dopant diffusion

Details Dual gate oxide formation with minimal channel dopant diffusion Dual gate oxide formation with minimal channel dopant diffusion

1998-10-13

2000-02-29

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438275, 438276, 438289, 438290, 438291, H01L 218238

Patent

active

060308621

ABSTRACT:
Sharply-defined dopant profiles in the transistor channel region of ultra high density semiconductor devices are maintained by selective transistor channel implants to reduce exposure to heat cycling, thereby reducing dopant diffusion. Embodiments include forming isolation regions on a semiconductor substrate, forming a relatively thick first gate dielectric layer, then performing transistor channel implantations. The first gate dielectric layer is then masked and etched, and a second, thinner gate dielectric layer is formed. The transistor channel implants are not affected by the temperature cycle of the first gate dielectric layer formation, thereby enabling dual gate dielectric formation without adversely affecting the electrical characteristics of the finished device.

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