Dual gate MOSFET fabrication method

Details Dual gate MOSFET fabrication method Dual gate MOSFET fabrication method

1999-02-03

2001-01-02

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S223000, C438S241000, C438S279000

Utility Patent

active

06168998

ABSTRACT:

This application claims the benefit of Korean patent application No. 6378/1998, filed Feb. 27, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dual gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and more particularly, to an improved fabrication method for the dual gate MOSFET.
2. Discussion of the Related Art
FIGS. 1A through 1D
are schematic cross-sectional views sequentially illustrating a fabricating method for a dual gate MOSFET according to a conventional method.
As shown in
FIG. 1A
, a gate oxide layer
13
is formed on a silicon substrate
11
. An undoped polysilicon layer
15
is formed on the gate oxide layer
13
.
A first photoresist pattern
17
is formed on the polysilicon layer
15
. The first photoresist pattern
17
is formed by patterning a first photoresist layer, exposing a portion of the undoped polysilicon layer
15
that will become an n-type polysilicon layer.
Subsequently, group V ions, such as P
+
or As
+
, are implanted into the exposed portion of the polysilicon layer
15
to form a doped polysilicon region
15
a
including n-type impurities.
As shown in
FIG. 1B
, the first photoresist pattern
17
is removed, and a second photoresist pattern
19
is formed on the undoped polysilicon layer
15
having the doped polysilicon region
15
a
formed therein. The second photoresist pattern
19
is formed by patterning a second photoresist layer, exposing a portion of the undoped polysilicon layer
15
that will become a p-type polysilicon layer.
Then, group III ions, such as B
+
or BF
2
+
, are implanted into the exposed portion of the polysilicon layer
15
to form a doped polysilicon region
15
b.
As shown in
FIG. 1C
, a pair of third photoresist patterns
21
are formed on the polysilicon layer
15
. The third photoresist patterns
21
are formed by patterning a third photoresist layer to correspond to gates, which are to be formed subsequently.
As illustrated in
FIG. 1D
, using the third photoresist patterns
21
as masks, the n-type and p-type ion-implanted polysilicon layer
15
and the gate oxide layer
13
are sequentially etched to form a first gate
22
and a second gate
23
. Then, the third photoresist patterns
21
are removed. The first and second gates
22
,
23
are therefore called dual gates.
However, according to the conventional dual gate fabrication method, the doped polysilicon regions
15
a
,
15
b
, which are doped differently from each other, are simultaneously etched using an identical etching technique to form the first and second gates
22
,
23
, whereby profiles of the first and second gates
22
,
23
are disadvantageously different from each other.
Further, it has been difficult to dope ions into the gates
22
,
23
when the gates
22
,
23
need to be made thin.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed a to dual gate MOSFET fabrication method that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a dual gate MOSFET fabricating method which forms a pair of dual gates with identical profiles during a fabrication process, and overcoming difficulties in ion-implanting by considering respective thicknesses of the gates.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In one aspect of the present invention there is provided a dual gate MOSFET fabrication method including the steps of forming a first insulation layer on a semiconductor substrate, forming a first polysilicon layer on the first insulation layer, forming a first photoresist pattern on the first polysilicon layer, forming a first gate by sequentially etching the first polysilicon layer and the first insulation layer by using the first photoresist pattern as a mask, removing the first photoresist pattern, forming a second insulation layer on the semiconductor substrate and the first gate, forming a second polysilicon layer on the second insulation layer, forming a second photoresist pattern on the second polysilicon layer, and forming a second gate by etching the second polysilicon layer and the second insulation layer by using the second photoresist pattern as a mask.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


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