Dual gate LDMOS device fabrication methods

Details Dual gate LDMOS device fabrication methods Dual gate LDMOS device fabrication methods

2007-01-25

2009-10-27

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21427

Reexamination Certificate

active

07608513

ABSTRACT:
An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42′) and is spaced apart from the wells (46, 46′, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42′) between the wells (46′, 44) or partly both. A second gate (G2) (66), spaced apart from G1(56), overlies the N-well (44). A body contact (74) to the substrate (42, 42′) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42′) to isolation wall (76) PN junction. When the body contact (74) is connected to G2(66), a predetermined static bias Vg2is provided to G2(66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.

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