Dual gate dielectric SRAM

Details Dual gate dielectric SRAM Dual gate dielectric SRAM

2007-06-07

2009-06-23

Weiss, Howard (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S478000, C365S185240

Reexamination Certificate

active

07550337

ABSTRACT:
An SRAM cell structure containing a PFET gate dielectric having a thicker effective oxide thickness (EOT) than an NFET gate dielectric and methods of manufacturing the same is provided. The PFET gate dielectric and the NFET gate dielectric may be silicon oxynitride layers, CVD oxide layers, or high-K dielectric layers having different thicknesses. The PFET gate dielectric may be a stack of two dielectric layers and the NFET gate dielectric may be one of the two dielectric layers. The greater EOT of the PFET gate dielectric produces reduction of the on-current of the pull-up PFETs for optimal SRAM performance.

REFERENCES:
patent: 6556477 (2003-04-01), Hsu et al.
patent: 6723661 (2004-04-01), Fitzergald
patent: 7217949 (2007-05-01), Chan et al.
patent: 7262987 (2007-08-01), Abadeer et al.
patent: 7295457 (2007-11-01), Chan et al.
patent: 7408800 (2008-08-01), Braceras et al.
patent: 2006/0084247 (2006-04-01), Liu
patent: 2006/0208323 (2006-09-01), Anderson et al.
patent: 2007/0164365 (2007-07-01), Chan et al.

Affiliated with

Also associated with

Rating

Dual gate dielectric SRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual gate dielectric SRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual gate dielectric SRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4068139