Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-05-10
2005-05-10
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S287000, C257S310000, C257S410000
Reexamination Certificate
active
06890811
ABSTRACT:
A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.
REFERENCES:
patent: 5960289 (1999-09-01), Tsui et al.
patent: 6159782 (2000-12-01), Xiang et al.
patent: 6211034 (2001-04-01), Visokay et al.
patent: 6248675 (2001-06-01), Xiang et al.
patent: 6265325 (2001-07-01), Cao et al.
patent: 6309936 (2001-10-01), Gardner et al.
patent: 6406956 (2002-06-01), Tsai et al.
patent: 6420742 (2002-07-01), Ahn et al.
patent: 6455330 (2002-09-01), Yao et al.
patent: 6482726 (2002-11-01), Aminpur et al.
Article “Outlook on New Transistor Materials,” by L. Peters in Semiconductor International, Oct. 1, 2001 edition.
Chen Chi-Chun
Chen Shih-Chang
Hou Tou-Hung
Wang Ming-Fang
Yang Chih-Wei
Haynes and Boone LLP
Picardat Kevin M.
LandOfFree
Dual gate dielectric scheme: SiON for high performance... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual gate dielectric scheme: SiON for high performance..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual gate dielectric scheme: SiON for high performance... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3423634