Dual gate dielectric scheme: SiON for high performance...

Details Dual gate dielectric scheme: SiON for high performance... Dual gate dielectric scheme: SiON for high performance...

2002-10-29

2004-03-16

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S240000, C438S287000

Reexamination Certificate

active

06706581

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of semiconductor manufacturing. In particular, the method involves forming two or more gate dielectric layers comprised of different materials during the fabrication of integrated circuits for system on a chip (SOC) technology.
BACKGROUND OF THE INVENTION
Complimentary metal oxide semiconductor (CMOS) field effect transistor (FET) technology is being driven to smaller gate electrode sizes by a constant demand for higher performance. As stated in an article “Outlook on New Transistor Materials” by L. Peters in Semiconductor International, Oct. 1, 2001 edition, the next generation 70 nm and 50 nm technology nodes will need new gate dielectric materials in order to accommodate a shrinking gate size. A high k dielectric option comprised of a metal oxide is a leading candidate to replace the traditional oxide or oxynitride layer. A higher k value in materials such as Ta
2
O
5
, TiO
2
, Al
2
O
3
, ZrO
2
, HfO
2
, Y
2
O
3
, L
2
O
5
and their aluminates and silicates will enable an increase in the physical dielectric thickness to suppress tunneling current which causes a high gate leakage current in transistors. The high k dielectric material can be formed as an amorphous layer or as a monocrystalline layer. The interfacial layer for the gate dielectric includes oxides, nitrides, oxynitrides, and aluminates. In some cases an interfacial layer is omitted and the gate dielectric material is formed directly on silicon.
The thickness of the gate oxide is critical to the performance of the device. There is a constant need for thinner oxides to allow a higher speed device with lower power consumption. Current technology requires gate oxide thicknesses of about 50 Angstroms or less. For ultra thin silicon dioxide gates, leakage current will increase tremendously as thickness is reduced. This will cause a large current in the standby mode (I
OFF
) and a large standby power consumption, thereby making products with these devices commercially unacceptable. Thus, new gate dielectric materials are required to suppress gate leakage as the gate dielectric thickness approaches 20 nm or less.
With the introduction of system on a chip (SOC) technology, there is a need to form multiple gate dielectric thicknesses on a substrate to enable different functions to perform simultaneously. For example, circuits for I/O connections, high performance devices, and low power devices must be fabricated on the same substrate. While low power circuits currently require an effective gate oxide thickness (EOT) of 12 to 15 Angstroms and high performance circuits need an EOT in the range of 8 to 12 Angstroms, the IC industry predicts the driver for high k dielectrics will be the low power application with an estimated EOT=1.8 nm in 2005. Silicon oxynitride (SiON) can function adequately as the gate dielectric for high performance devices until 2005, but for low power devices the switch to high k dielectrics must occur for an EOT <17 Angstroms in order to satisfy the leakage requirements.
A method for forming dual gate oxide layers having different thicknesses is described in U.S. Pat. No. 6,265,325 in which a field oxide separates two device areas. After a thermal oxide layer is grown and a polysilicon layer is deposited, a photoresist mask is used to selectively uncover the substrate in one device area. A second oxide layer is grown that is thinner than the first oxide. Then a second polysilicon layer is formed over both device areas. A planarization step is employed to make the second polysilicon layer coplanar with the first polysilicon layer.
Another method for fabricating a dual oxide gate structure is provided in U.S. Pat. No. 5,960,289. An oxide in the range of 50 to 240 Angstroms thick is grown between shallow trench isolation (STI) regions and is protected by subsequently depositing a thin silicon oxynitride (SiON) layer. A photoresist layer is coated and patterned and serves as an etch mask for selectively removing the SiO
2
and SiON over one device region. A thin oxide which is 20 to 60 Angstroms thick is then grown over the exposed device region while SiON prevents any additional oxide growth on the other device region. This prior art and the previous case do not address extendibility to gate dielectric thicknesses less than 20 Angstroms where high k dielectric materials will be needed.
Related U.S. Pat. Nos. 6,159,782 and 6,248,675 introduce a high k dielectric approach for manufacturing an N-channel MOSFET and a P-channel MOSFET on the same substrate. High temperature processes such as activation anneal of implanted ions and silicidation anneal are performed on a dummy gate electrode and sacrificial gate dielectric so as to preserve the integrity of a Ta
2
O
5
high k dielectric that is deposited later and is sensitive to temperatures over 800° C. Once the dummy gate electrode is removed by etching to form a gate opening, a conformal layer of SiON is deposited followed by a conformal layer of Ta
2
O
5
. The opening is filled with amorphous silicon, planarized, and is then annealed at <600° C. to produce a permanent gate electrode. However, the method does not teach how to form a dielectric layer for a high performance device and a high k dielectric layer for a low power device on the same substrate for a SOC application.
Therefore, a method is needed whereby a gate dielectric layer with an EOT of less than 10 nm for a high performance device and a high k dielectric layer with an EOT preferably <10 nm for a low power device can be formed on the same substrate for current and future SOC applications.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a method of forming a SiON dielectric layer and a high k dielectric layer on the same substrate during the fabrication of a semiconductor device, micro-electromechanical (MEMS) device, or other device requiring the formation of a gate electrode on a substrate.
A further objective of the present invention is to provide a method of forming a high k dielectric layer that is scalable to the 70 nm and 50 nm technology nodes, preferably with an EOT that is <1.8 nm for a low power device.
A still further objective of the present invention is to provide a dual gate dielectric scheme that is compatible with a conventional dual or triple thickness SiO
2
process. A still further objective is to provide an efficient, low cost dual gate dielectric process in which the high k dielectric layer can be annealed simultaneously with the growth of the second dielectric layer.
These objectives are achieved by first providing a substrate with device areas separated by regions of insulating material such as STI features. In the first embodiment, an interfacial layer comprised of SiO
2
, SiON, or Si
3
N
4
is deposited on the substrate. A high k dielectric material is then deposited by a chemical vapor deposition (CVD), metal-organic CVD (MOCVD), or atomic layer CVD (ALD) process. The high k dielectric material is selected from a group of metal oxides including Ta
2
O
5
, TiO
2
, Al
2
O
3
, ZrO
2
, HfO
2
, Y
2
O
3
, L
2
O
3
and their aluminates and silicates. The high k dielectric material may comprise a single layer of one metal oxide or several layers including two or more metal oxides. A photoresist is coated and patterned on the high k dielectric layer to uncover the substrate in a region that will form the high performance device. After the high k dielectric and interfacial layers are removed in exposed regions, the photoresist is stripped and the substrate is cleaned. An ultra thin SiON layer with an EOT of preferably <10 nm is then deposited by using a silicon source gas in combination with NH
3
, NO or N
2
with O
2
. During the deposition of the second dielectric layer, the high k dielectric layer is annealed in an in-situ process. A post-deposition anneal involving NH
3
or a nitrogen containing gas may be added to further reduce leakage current and lower EOT. Conventional processing is followed to complete the construction of a MOSFET that is a low power dev

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