Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-31
2003-08-05
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S233000, C438S283000, C438S424000
Reexamination Certificate
active
06602746
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dual-gate CMOS semiconductor device and a dual-gate CMOS semiconductor device manufacturing method. More specifically, the present invention relates to a dual-gate CMOS semiconductor device and a dual-gate CMOS semiconductor device manufacturing method capable of reducing the mutual diffusion of impurities in a gate electrode.
2. Description of Related Art
In recent years, CMOS semiconductor devices of a dual-gate structure have been adopted with a view of improving performance and reducing power consumption. As the gate electrodes of this dual-gate structure, a polycrystalline silicon layer containing N type impurities such as arsenic is used on an NMOS part and a polycrystalline silicon layer containing P type impurities such as boron is used on a PMOS part.
The semiconductor device of such a dual-gate structure is disclosed by, for example, “M. Togo, et al., Thermal Robust Dual-Gate CMOs Integration Technologies for High-Performance DRAM-Embedded ASCIs', IEDM Technical Digest, p. 49 (1999)”.
According to the above-cited document, a so-called W polyside structure in which a WSi2 layer is built up on a polycrystalline silicon layer, is used as a gate electrode. This gate electrode is normally employed in a device having a mixture of a DRAM and Logic. In addition, for the purpose of realizing higher integration, a so-called SAC structure for providing contacts on a source/drain layer in a self-aligned manner to a gate electrode by forming a nitride film on the WSi2 layer and also forming a nitride film on a sidewall.
The conventional dual-gate CMOS semiconductor device, however, has the following disadvantages. A heat treatment is conducted to form elements after the formation of a gate electrode. Due to this, impurities contained in a polycrystalline silicon layer on an NMOS part and those contained in a polycrystalline silicon layer on a PMOS part are mutually diffused through the WSi2 layer. In other words, N type impurities are introduced into the polycrystalline silicon layer on the PMOS part and P type impurities are introduced into the polycrystalline silicon layer on the NMOS part, with the result that the performance of the semiconductor device disadvantageously deteriorates.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a novel, improved dual-gate CMOS semiconductor device and a manufacturing method therefor capable of suppressing the mutual diffusion of P type impurities and N type impurities in polycrystalline silicon layers on a gate electrode.
To obtain the above object, a typical invention of the present invention provides a dual-gate CMOS semiconductor device characterized by comprising: an NMOS part and a PMOS part formed on a semiconductor substrate; and a gate electrode formed on the NMOS part and the PMOS part, and constituted out of a polycrystalline silicon layer and a first conductive layer, and characterized in that the polycrystalline silicon layer is constituted out of a polycrystalline silicon layer containing N type impurities and a polycrystalline silicon layer containing P type impurities; and the first conductive layer has a groove region on a predetermined region including a boundary between the polycrystalline silicon layer containing the N type impurities and the polycrystalline silicon layer containing the P type impurities, the first conductive layer not being formed in the groove region.
According to the above-stated invention, the first conductive layer on the PMOS part and the first conductive layer on the NMOS part are isolated from each other by the formation of the groove region. It is, therefore, possible to reduce the mutual diffusion of the P type impurities and the N type impurities in the polycrystalline silicon layers.
“Furthermore, to obtain the above object, another typical invention of the present application provides a dual-gate CMOS semiconductor device manufacturing method characterized by: forming a P well and an N well on a semiconductor substrate using a first masking pattern; forming a gate insulating film on the P well and the N well formed on the semiconductor substrate; forming a polycrystalline silicon layer constituted out of a polycrystalline silicon layer containing N type impurities and a polycrystalline silicon layer containing P type impurities, on the gate insulating film; forming a first conductive layer on an entire surface on the polycrystalline silicon layer; removing the first conductive layer on a predetermined region including a boundary between the polycrystalline silicon layer containing the N type impurities and the polycrystalline silicon layer containing the P type impurities while using a second masking pattern, and thereby forming a groove region; forming a gate electrode by a photolithographic method and an etching method; and forming a source/drain layer on each of the P well and the N well by the photolithographic method and an ion implantation method, after forming the gate electrode.”
The above-stated invention can provide a semiconductor device wherein the first conductive layer on the PMOS part is isolated from the first conductive layer on the NMOS part by a boundary portion. As a result, it is possible to reduce the mutual diffusion of the P type impurities and the N type impurities in the polycrystalline silicon layers through the first conductive layers.
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Fourson George
Oki Electric Industry Co. Ltd.
Pham Thanh
Volentine & Francos, PLLC
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