Dual-edge triggered dynamic logic

Details Dual-edge triggered dynamic logic Dual-edge triggered dynamic logic

2001-05-14

2002-07-30

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S119000, C326S121000, C327S115000, C327S117000

Reexamination Certificate

active

06426652

ABSTRACT:

BACKGROUND OF THE INVENTION
The design of a computer system may be broken down into three parts system design, logic design, and circuit design. System design involves breaking the overall system into subsystems and specifying the characteristics of each subsystem. For example, system design of a computer system could involve specifying the number and type of memory units, arithmetic units, and input-output devices as well as the interconnection and control of these subsystems. Logic design involves determining how to interconnect basic logic building blocks to perform a specific function. An example of logic design is determining the interconnection of logic gates and flip-flops to perform binary addition. Circuit design involves specifying the interconnection of specific components such as resistors, diodes, and transistors to form a gate, flip-flop, or other logic building block.
There are various logic families that are used in circuit design. Each family has its own capabilities and limitations. Diode logic (“DL”) families use diodes to perform certain logic functions. The use of DL families is simple and inexpensive, and can be used effectively in specific situations. Resistor-transistor logic (“RTL”) families use resistors to combine multiple input signals and a transistor to amplify and invert the resulting combined signal. Like the DL families, the use of RTL families is simple and inexpensive. In addition, they are also useful because both normal and inverted signals are usually available. Diode-transistor logic (“DTL”) families use DL combined with a transistor at the output in order to provide logic inversion and to restore a signal to full logic levels. Transistor-transistor logic (“TTL”) families replace all input diodes in DTL with transistors. Emitter-coupled logic (“ECL”) families are designed to operate at extremely high speeds by avoiding delays that are inherent when a transistor becomes saturated. Complementary metal-oxide-semiconductor (“CMOS”) logic families use metal-oxide-semiconductor field-effect transistors (“MOSFETs”).
The use of MOSFET transistors is beneficial because lower currents are needed to operate these transistors than other types of devices. However, MOSFETs operate slower than devices used in other logic families. MOSFETs may be divided into two types of transistors: positive-channel metal-oxide semiconductor (“PMOS”) transistors and negative-channel metal-oxide semiconductor (“NMOS”) transistors. A transistor is ‘on’ when there is an electrical pathway across the transistor such that a voltage at one terminal of the transistor can be seen at another terminal of the transistor. NMOS transistors can be switched ‘on’ or ‘off’ by the movement of electrons, whereas PMOS transistors can be switched ‘on’ or ‘off’ by the movement of electron vacancies. Every MOSFET has a voltage threshold (“V
T
”) value, which is the voltage level at which the MOSFET switches ‘on’ or ‘off.’ Generally, a NMOS transistor switches ‘on’ when there is a high voltage applied to a gate terminal of the NMOS transistor and a PMOS transistor switches ‘on’ when there is a low voltage, e.g., ground, applied to a gate terminal of the PMOS transistor. Moreover, for the purposes of this application, the gate terminal of a MOSFET transistor will be referred to as the “input” of the transistor.
Like other logic families, CMOS logic families may be divided into two categories: static logic and dynamic logic. Static logic is logic in which the function of a circuit is not synchronized by a global signal, e.g., a clock signal. The output of the circuit is solely a function of the input to the circuit. Moreover, the output is asynchronous with respect to the input. Dynamic logic is logic in which the output of a circuit is synchronized by a global signal. Therefore, the output of a dynamic circuit is a function of both the input(s) to the circuit and the global signal.
An example of a CMOS logic family is CMOS buffer logic. Buffer logic is necessary in order to restore signals to full voltage levels. For example, a signal that should be at 5 volts may only be at 4 volts at a specific point in a circuit due to voltage dissipation. In order to ensure that a signal is at its true desired voltage level, a buffer inputs the signal and outputs a restored signal with a full voltage level. Alternatively, buffer logic can also be used to restore a 0 volt signal. Also, buffer logic can be used to set a signal to a desired voltage that is different in value from a full voltage level value.
FIG. 1
shows a prior art embodiment of static buffer logic that uses CMOS transistors. The static buffer (
10
) includes an input, INPUT_
1
, followed by two cascaded transistor pairs. The first pair of transistors (“the first pair”), the pair of transistors that immediately follows INPUT_
1
, includes a PMOS transistor (
12
) (referred to hereafter as “the PMOS transistor (
12
) in the first pair”) and a NMOS transistor (
14
) (referred to hereafter as “the NMOS transistor (
14
) in the first pair”). INPUT_
1
serves as an input to both the PMOS transistor (
12
) in the first pair and the NMOS transistor (
14
) in the first pair. The PMOS transistor (
12
) in the first pair has a terminal connected to a voltage source (
13
) (also referred to as “connected to high”) and another terminal that is connected to both a terminal of the NMOS transistor (
14
) in the first pair and a node, BUFFER_NODE_
1
. The NMOS transistor (
14
) in the first pair, in addition to having a terminal that is connected to both a terminal of the PMOS transistor (
12
) in the first pair and BUFFER_NODE_
1
, has another terminal connected to ground (
15
) (also referred to as “connected to low”).
The second pair of transistors (“the second pair”), the pair of transistors that follows the first pair of transistors, also includes a PMOS transistor (
16
) (referred to hereafter as “the PMOS transistor (
16
) in the second pair) and a NMOS transistor (
18
) (referred to hereafter as “the NMOS transistor (
18
) in the second pair”). BUFFER_NODE_
1
serves as an input to both the PMOS transistor (
16
) in the second pair and the NMOS transistor (
18
) in the second pair. The PMOS transistor (
16
) in the second pair has a terminal connected to high (
13
) and another terminal that is connected to both a terminal of the NMOS transistor (
18
) in the second pair and the output of the static buffer (
10
), OUTPUT_
1
. The NMOS transistor (
18
) in the second pair, in addition to having a terminal that is connected to the PMOS transistor (
16
) in the second pair and OUTPUT_
1
, has another terminal connected to low (
15
).
When there is a rising edge, i.e., high, at INPUT_
1
, the PMOS transistor (
12
) in the first pair switches ‘off’ and the NMOS transistor (
14
) in the first pair switches ‘on.’ Since the NMOS transistor (
14
) in the first pair switches ‘on,’ BUFFER_NODE_
1
gets connected to low (
15
) through the NMOS transistor (
14
) in the first pair. As BUFFER_NODE_
1
goes low, the PMOS transistor (
16
) in the second pair switches ‘on’ and the NMOS transistor (
18
) in the second pair switches ‘off.’ Since the PMOS transistor (
16
) in the second pair switches ‘on,’ OUTPUT_
1
gets connected to high (
13
) through the PMOS transistor (
16
) in the second pair. Therefore, when INPUT_
1
goes high, OUTPUT_
1
follows and goes high restoring any voltage dissipation that may have been present at INPUT_
1
.
Alternatively, when there is a falling edge, i.e., low, at INPUT_
1
, the PMOS transistor (
12
) in the first pair switches ‘on’ and the NMOS transistor (
14
) in the first pair switches ‘off.’ Since the PMOS transistor (
12
) in the first pair switches ‘on,’ BUFFER_NODE_
1
gets connected to high (
13
) through the PMOS transistor (
12
) in the first pair. As BUFFER_NODE_
1
goes high, the PMOS transistor (
16
) in the second pair switches ‘off’ and the NMOS transistor (
18
) in the second pair switches ‘on.’ Since the NMOS transistor (
18
) in the second pair switches ‘on,’ OUTPUT_
1
gets connected to low (
15
) through the NMO

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