Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-13
2004-11-23
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S217000
Reexamination Certificate
active
06821852
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuits and, more specifically, to methods of forming dual doped gate structures in an integrated circuit.
BACKGROUND OF THE INVENTION
As the density of devices, such as resistors, capacitors, and transistors, in an integrated circuit is increased, the processes for manufacturing the circuit become more complex, and in general, the number of manufacturing operations and mask steps required to fabricate the integrated circuit increases. The number of mask steps used to manufacture an integrated circuit is one measure of the complexity of the manufacturing process. Dual doped gate integrated circuit structures have been manufactured using four mask, three mask, and two mask processes.
FIGS. 1A-1D
illustrate a prior art four mask process for manufacturing a dual doped gate circuit structure in a substrate
101
. In a first masked implant operation, illustrated in
FIG. 1A
, an opening
103
in a resist structure
105
defines a first implant area in the substrate
101
. A deep PWELL implant forms PWELL
107
and a shallow n-channel threshold voltage (V
T
) adjust implant forms an n-channel threshold voltage (V
T
) adjust area
109
. In a second masked implant operation, illustrated in
FIG. 1B
, an opening
111
in a resist structure
113
defines a second implant area in the substrate
101
. A deep NWELL implant forms an NWELL
115
. A shallow p-channel threshold voltage (V
T
) adjust implant forms a p-channel threshold voltage (V
T
) adjust area
117
. After the first and second masked implant operations, a sacrificial oxide
119
is removed from a surface of the substrate
101
. A gate oxide layer
121
and a polysilicon gate layer
123
are formed on a surface of the substrate
101
, as illustrated in FIG.
1
C. In a third masked implant operation, illustrated in
FIG. 1C
, an opening
124
in a resist structure
125
defines a third implant area in the substrate
101
. An n
+
implant forms an n
+
polysilicon region
127
in the polysilicon layer
123
over the PWELL
107
. In a fourth masked implant operation, illustrated in
FIG. 1D
, an opening
129
in the resist structure
131
defines a fourth implant area in the substrate
101
. A p
+
implant forms a p
+
polysilicon region in the polysilicon layer
133
over the NWELL
115
.
FIGS. 2A-2D
illustrate a prior art three mask process for manufacturing a dual doped gate circuit structure in a substrate
201
. In a blanket implant operation, illustrated in
FIG. 2A
, a deep blanket PWELL implant forms a blanket PWELL
203
and a shallow blanket n-channel threshold voltage (V
T
) adjust implant forms an n-channel threshold voltage (V
T
) adjust area
205
. In a first masked implant operation, illustrated in
FIG. 2B
, an opening
207
in a resist structure
209
defines an implant area in substrate
201
. A deep NWELL implant forms an NWELL
211
, and a shallow p-channel threshold voltage adjust implant forms p-channel threshold voltage (V
T
) adjust area
213
. After the first implant operation and the second masked implant operation, a sacrificial oxide layer
215
is removed from a surface of the substrate
201
and a gate oxide layer
217
and a polysilicon layer
219
are formed on the surface of the substrate
201
. In a second masked implant operation, illustrated in
FIG. 2C
, an opening
220
in a resist structure
221
defines an implant area in substrate
201
. An n
+
implant forms an n
+
polysilicon layer
225
over the PWELL
203
. In the third masked implant operation, illustrated in
FIG. 2D
, an opening
227
in a resist structure
229
defines an implant area, and a p
+
implant forms a p
+
polysilicon
231
over the NWELL
211
.
FIGS. 3A and 3B
illustrate a prior art two mask process for manufacturing a dual doped gate circuit structure in a substrate
301
. For a first masked implant operation, illustrated in
FIG. 3A
, an opening
303
in a resist structure
305
defines an implant area in substrate
301
. The implant area includes a gate oxide layer
307
and a polysilicon layer
309
formed in the substrate
301
. A deep p-type PWELL implant into the substrate
301
forms a PWELL
303
, a shallow p-type threshold voltage (V
T
) adjust implant into substrate
301
forms a shallow p-type threshold voltage (V
T
) adjust region
311
, and a shallow n
+
implant into the polysilicon layer
309
forms an n
+
polysilicon region
313
in the polysilicon layer
309
. For a second masked implant operation, illustrated in
FIG. 3B
, an opening
315
in the resist structure
317
defines an implant area. The implant area includes the gate oxide layer
307
and the polysilicon layer
309
formed above the substrate
301
. A deep n-type NWELL implant into the substrate
301
forms an NWELL
317
, a shallow n-type threshold voltage (V
T
) adjust implant into the substrate
301
forms a shallow n-type threshold voltage (V
T
) adjust region
319
, and a shallow p
+
implant into the polysilicon layer
309
forms a p
+
polysilicon region
321
in the polysilicon layer
309
.
Unfortunately, each masking operation used in the manufacturing of the dual doped gate structure described above adds expense to the manufacturing process. The expense includes both the direct cost of the masking operation and the cost related to a longer manufacturing cycle.
For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
The above mentioned problems with the fabrication of dual doped gates and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The present invention provides a method for forming an integrated circuit dual gate structure using only one mask. In one embodiment of the present invention, a substrate is prepared and one or more dual gate structures is formed in the substrate using only one mask. In an alternate embodiment of the present invention, a substrate is prepared, a first gate structure having a PWELL is formed without using a mask, and a second gate structure having an NWELL is formed using only one mask. In another alternate embodiment of the present invention, a substrate is prepared, a first gate structure having an NWELL is formed without using a mask, and a second gate structure having a PWELL is formed using only one mask.
These and other embodiments, aspects, advantages and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages and features of the invention are realized and attained by means of the instrumentalities, procedures and combinations particularly pointed out in the appended claims.
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Micro)n Technology, Inc.
Pham Long
Schwegman Lundberg Woessner & Kluth P.A.
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