Dual damascene wiring and method

Details Dual damascene wiring and method Dual damascene wiring and method

2007-05-29

2007-05-29

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S584000, C257SE21577

Reexamination Certificate

active

10710478

ABSTRACT:
A structure and method of fabricating a dual damascene interconnect structure, the structure including a dual damascene wire in a dielectric layer, the dual damascene wires extending a distance into the dielectric layer less than the thickness of the dielectric layer and dual damascene via bars integral with and extending from bottom surfaces of the dual damascene wires to a bottom surface of the dielectric layer.

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patent: 2003/0139034 (2003-07-01), Yuang
patent: 1154467 (2001-11-01), None
R. F. Schnabel et al., Slotted Vias for Dual Damascene Interconnects in 1Gb DRAMs, 1999 Symposium on VLSI Technology Digest of Technical Papers, pp. 43-44.

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