Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2007-02-27
2007-02-27
Schillinger, Laura M. (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S738000, C438S740000, C438S700000
Reexamination Certificate
active
10765072
ABSTRACT:
A dual damascene interconnect structure, produced using etch chemistry based on C2H2F4, includes (i) an etch stop layer of either undoped silicon oxide or doped silicon oxide, and (ii) dielectric layers both above and below the etch stop layer of the other (i.e., when the etch stop layer comprises undoped silicon oxide, the dielectric layers above and below the etch stop layer independently comprise a doped silicon oxide; and when the etch stop layer comprises doped silicon oxide, the dielectric layers above and below the etch stop layer independently comprise an undoped silicon oxide).
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