Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-07-30
2000-10-31
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438701, 438638, H01L 214763
Patent
active
061402265
ABSTRACT:
The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.
REFERENCES:
patent: 5604156 (1997-02-01), Chung et al.
patent: 5882996 (1999-03-01), Dai
Grill Alfred
Hummel John Patrick
Jahnes Christopher Vincent
Patel Vishnubhai Vitthalbhai
Saenger Katherine Lynn
Everhart Caridad
International Business Machines - Corporation
Trepp Robert M.
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