Dual damascene process without an etch stop layer

Details Dual damascene process without an etch stop layer Dual damascene process without an etch stop layer

2005-12-05

2009-12-08

Nguyen, Kimberly D (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257SE21575, C257SE21597

Reexamination Certificate

active

07629690

ABSTRACT:
A non-ESL semiconductor interconnection structure and a method of forming the same are provided. The non-ESL semiconductor interconnection structure includes a first low-k dielectric layer comprising a first region and a second region overlying the substrate, a plurality of conductive features in the first low-k dielectric layer, a cap layer on at least a portion of the conductive features, and a dielectric capping layer overlying the first low-k dielectric layer in the second region but not in the first region. The conductive features in the second region have a substantially greater spacing than the conductive features in the first region. The dielectric capping layer preferably has an inherent compressive stress.

REFERENCES:
patent: 6417094 (2002-07-01), Zhao et al.
patent: 6472306 (2002-10-01), Lee et al.
patent: 2004/0251549 (2004-12-01), Huang et al.
patent: 2006/0234443 (2006-10-01), Yang et al.

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