Dual damascene process using high selectivity boundary layers

Details Dual damascene process using high selectivity boundary layers Dual damascene process using high selectivity boundary layers

1998-07-02

2000-02-15

Tsai, Jey

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438624, 438626, 438629, 438634, 438637, 438638, 438666, 438667, 438668, 438669, 438672, 438675, H01L 214763

Patent

active

060252596

ABSTRACT:
A method of manufacturing a semiconductor device with multiple dual damascene structures that maintains the maximum density. A first dual damascene structure having a first via and a first trench is formed in a first interlayer dielectric and a first etch stop layer formed on the planarized surface of the first interlayer dielectric. Two layers of interlayer dielectric separated by a second etch stop layer is formed on the surface of the first etch stop layer. A third etch stop layer is formed on the upper layer of interlayer dielectric and a first photoresist layer formed on the third etch stop layer. The photoresist layer is etched having a dimension coinciding with a width dimension of the first via. The third etch stop layer is selectively etched and the first photoresist layer removed and replaced by a second photoresist layer. The second photoresist layer is etched having a dimension coinciding with a width dimension of the first trench. The two layers of interlayer dielectric and the first, second and third etch stop layers are etched to form a second dual damascene structure having a second via and a second trench having the same dimensions as the first dual damascene structure.

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