Dual damascene process to reduce etch barrier thickness

Details Dual damascene process to reduce etch barrier thickness Dual damascene process to reduce etch barrier thickness

1999-09-27

2002-08-06

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S634000

Reexamination Certificate

active

06429119

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation dual damascene structures are described which use thin etch stop-layers or etch barriers, which lowers parasitic capacitance of the interconnect wiring.
As a background to the current invention, the damascene processing is an alternative method for fabricating planar interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide RIE, then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices. In both examples, sputtered Ti/TiN liners have been coated with chemical vapor deposited (CVD) W metal, then polished back to oxide.
The damascene approach has been adopted in many applications, since it efficiently provides the high yield and large process windows required for volume manufacturing. The use of CMP leads to a decrease in the number of interlevel shorts and lowers defect densities, since unwanted surface material is easily removed. Upon completion of CMP, the wafer surface is returned in a globally planar state, extending process windows for subsequent process steps, i.e., lithographic, etching, and CMP processing steps.
Key to the damascene processing approach is that the deposited conductive metal is deposited into a previously deposited patterned insulator. This is desirable because mask alignment, dimensional control, rework, and the etching process are all easier when applied to a dielectric rather than metal films. Damascene processing achieves these benefits by shifting the enhanced filling and planarization requirements from dielectric to metal films, and by shifting control over interconnect thickness from metal deposition to insulator patterning and metal CMP.
Sputter deposition has some key advantages as a metal deposition technique because it can be used to deposit many conductive materials, at high deposition rates, with good uniformity and low cost of ownership. Conventional sputtering does not fill or coat recessed features well. Sputtered atoms are typically ejected from a target in all directions, though the degree of flux directionality depends on the specific material being deposited, and on deposition conditions. Conventional sputtering fill is poorer for deeper, narrower (high-aspect-ratio) features. In addition, fill is especially bad for corners of recesses, which have relatively small acceptance angles for flux, and for thick depositions, since the upper surface deposition can block incoming flux and produce a void in the recessed feature.
The fill factor by sputter deposition has been significantly improved by collimating the sputtered flux. A collimated flux is produced by removing sputtered flux that approaches the substrate at a large angle from the surface normal. Typically, this is achieved by inserting between the target and substrate a collimator plate having an array of hexagonal cells.
Collimated sputtering is acceptable for thin liner depositions to cover features having moderate aspect ratios, but is not an appropriate technique for the complete filling of such features. Instead, for short-distance wiring such as studs and bit lines for which the high conductivity of Al is not required, chemical-vapor-deposited (CVD) W has proven to be a robust process that integrates easily with liner deposition and CMP to provide a manufacturing interconnect module. In addition, the W is easily patterned using CMP since it is hard and corrosion-resistant. It is also compatible with RIE formation of overlying Al-based wires, since it offers excellent etch selectivity in the preferred Cl-based chemistries.
Chemical vapor deposition (CVD) of W usually requires an underlying conductive barrier and “seed” layers to prevent consumption of substrate Si from reaction with WF
6
at the contact level, and to promote distributed nucleation and low contact resistance. A layer of Ti is used since it provides good adhesion and low contact resistance. However, the Ti alone is not sufficient, because the F from the WF
6
reacts with the Ti and produces a brittle, high-resistivity compound. However, the use of a TiN film between the Ti and W solves these problems by enhancing W nucleation while preventing the reaction of F with the Ti or any exposed Si. A W seed layer is then formed on the TiN.
Since Ti-based liners are less conductive and less easily polished than W, it is desirable to keep the liners as thin as possible. However, since the sputtered (PVD) liners are not conformal, inadequate coverage of recesses or foreign material defects can allow F to react with the underlying Ti, causing the liners to detach from their substrate. The TiN layer can crack and curl up, since the film is in tension. The CVD W can then deposit on the rolled-up TiN and these formations are termed tungsten “mounds” or “mushrooms”. Improvements in commercial process equipment have improved the CVD liners, for example, the CVD TiN and Ti processes. Furthermore, CVD Ti and TiN offer good conformality, but require higher deposition temperatures and contain higher levels of impurities than do the sputtered (PVD) films.
After deposition, CMP is applied to complete the inlaid structure. In the CMP process, material is removed from the wafer through the combined effects of a polish pad and an abrasive slurry. The chemical dissolution of material is aided by a mechanical component which is useful in removing passivating surface layers. Chemical and mechanical selectivity's between materials are desired, since CMP must remove the metal overburden without removing appreciable amounts of inlaid metal or reducing interconnect thickness.
Scratching of the polished surface must also be avoided. Scratches in the inlaid metal can reduce the cross section locally, resulting in an elevated current density and/or elevated stress, thereby accelerating interconnect failures.
In the dual-damascene process, a monolithic stud/wire structure is formed from the repeated patterning of a single thick oxide film followed by metal filling and CMP. First, a relatively thick oxide layer is deposited on a planar surface. The oxide thickness is slightly larger than the desired final thickness of the stud and wire, since a small amount of oxide is removed during CMP. Stud recesses are formed in the oxide using photolithography and RIE that either partially etches through the oxide or traverses the oxide and stops on the underlying metal to be contacted. The wire recesses can then be formed using a separate photolithography step and a timed oxide etching step. If the former stud RIE option is used, the wire etching completes the drilling of the stud holes.
Alternatively, the wire recesses can be formed first, but this approach makes the photolithography for the studs more difficult, since the resulting surface is less planar. Next, the stud/wire metallization is deposited, then planarized using CMP. The resulting interconnects are produced with fewer process steps than with conventional processing and with the dual damascene process, two layer of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
The dual-damascene process can be more difficult to fill and planarization than the single-damascene processing. Specifically, the metal films must now fill features having aspect ratios much greater than 1. This can be attained with CVD W, provided the adhesive liner covers the recessed surfaces. To obtain adequate liner coverage using collimated sputtered (PVD) Ti/TiN liners, a larger liner thickness must be applied, which is then difficult to polish away, without dishing (W dishing due to its e

Affiliated with

Also associated with

Rating

Dual damascene process to reduce etch barrier thickness does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual damascene process to reduce etch barrier thickness, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual damascene process to reduce etch barrier thickness will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2950544