Dual-damascene process to fabricate thick wire structure

Details Dual-damascene process to fabricate thick wire structure Dual-damascene process to fabricate thick wire structure

2006-01-19

2009-10-13

Purvis, Sue (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257SE23142

Reexamination Certificate

active

07602068

ABSTRACT:
A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.

REFERENCES:
patent: 5763010 (1998-06-01), Guo et al.
patent: 6143640 (2000-11-01), Cronin et al.
patent: 6383920 (2002-05-01), Wang et al.
patent: 6429119 (2002-08-01), Chao et al.
patent: 6466427 (2002-10-01), Chen
patent: 6797630 (2004-09-01), Wu et al.
patent: 6828245 (2004-12-01), Chang
patent: 2001/0054730 (2001-12-01), Kim et al.
patent: 2004/0094821 (2004-05-01), Lur et al.
patent: 2004/0256654 (2004-12-01), Korner et al.
patent: 2005/0054194 (2005-03-01), Tsai et al.

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