Dual damascene process for carbon-based low-K materials

Details Dual damascene process for carbon-based low-K materials Dual damascene process for carbon-based low-K materials

1999-10-29

2001-04-03

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S636000, C438S638000

Reexamination Certificate

active

06211061

ABSTRACT:

DESCRIPTION OF THE PRIOR ART
In current IC fabrication, connections between metal levels, such as copper, which are separated by dielectric interlevels, are typically formed with a damascene method of via formation between metal levels. The first metal pattern is first completely covered with dielectric, such as silicon dioxide. A trench is patterned into the dielectric layer. A via is patterned from the trench, through the dielectric layer, to the first metal pattern. A metal film, such as copper, is then used to fill the via and the trench. A layer consisting of dielectric with a metal via through it now overlies the first metal pattern. The excess metal can be removed using a CMP process, as is well known in the art. The result is an “inlaid”, or damascene metal structure.
As devices continue to be smaller, less expensive, and more powerful, smaller geometries and denser packaging are required for integrated circuits. Conductors having high resistivity create conduction paths with high impedence and large propagation delays, resulting in shorter device life and reliability problems. High-K dielectrics have cause high capacitance resulting in shorter device life and reliability problems. Copper is a particularly attractive material for use in interconnects and vias, due to its high conductivity. Organic low-K materials such as FLARE, SILK, and PAE are attractive for use as dielectrics, due to the reduced capacitance. However, there are fabrication problems associated with a copper dual damascene process with an organic, low-K dielectric material, due to the lack of etch selectivity between the organic, low-K dielectric material and bottom anti-reflective coating (barc), and due to the undesireability of using a high-K etch stop layer.
A first dual damascene process known to the inventors is a via first with barc filling. In this process, a via opening is formed through the inter-metal dielectric layer (IMD) before a trench is formed. A bottom anti-reflective coating (barc) is deposited in the via opening and over the IMD. The IMD is then patterned to form a trench, using photolithography and etching. The barc is also removed during this etch. However, for dielectric layers composed of organic, low-K materials, there is not sufficient etch selectivity between the organic low-K material and the barc. If barc material remains it can not easily be removed.
A second dual damasene process known to the inventors is a partial via first without barc filling. In this process, a via opening is formed part-way through the inter-metal dielectric layer (IMD) before a trench is formed. Because the underlying metal level is not exposed, no barc is used. However, to prevent faceting at the edge of the via opening during trench etching for an organic, low-K dielectric material, an additional high-K etch stop layer is required at the intended level for the bottom of the trench.
A third dual damascene process known to the inventors is a self-aligned dual damascene process, wherein the via is formed first. In this process, a lower IMD layer and an overlying hard mask are patterned to form a via opening through the lower IMD layer and an overlying hard mask to the underlying first metal level. Then an upper IMD layer is formed over the hard mask and in the via opening. A trench pattern is formed in the upper IMD layer, stopping at the hard mask, except where the via opening was formed in the hard mask; thereby forming a dual damascene opening for the trench and via. However, for an organic low-K dielectric material, a high-K material hard mask is required to provide etch selectivity between the hard mask and the organic, low-K dielectric layer.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,904,565 (Nguyen et al.) shows a dual damascene process using barrier layers and forming via and trench steps.
U.S. Pat. No. 5,529,953 (Shoda) shows a dual damascene shaped opening, selective deposition of conductive layers having different deposition times for tungsten at the bottom of the contact hole and at the bottom of the trench; thereby allowing the damascene structure to be formed without voids or cracks.
U.S. Pat. No. 5,863,835 (Yoo et al.) shows a dual damascene shaped interconnect by forming and filling a contact hole opening to form a contact plug in an IMD layer, then forming and filling an interconnect region surrounding the top portion of the contact plug.
U.S. Pat. No. 5,869,395 (Yim) shows a dual damascene process using a barrier layer.
U.S. Pat. No. 5,741,626 (Jain et al.) teaches a dual damascene process using an etch barrier between IMD
1
& IMD
2
.
U.S. Pat. No. 5,635,423 (Huang et al.) and U.S. Pat. No. 5,686,354 (Avanzino et al.) show other dual damascene processes.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a dual damascene structure in a carbon-based, low-K material.
It is another object of the present invention to provide a method for forming a copper dual damasene structure in a carbon-based, low-K material without faceting at the edge of the via opening, and without using a high-K etch stop layer.
It is yet another object of the present invention to provide a method for forming a dual damascene structure in a carbon-based, low-K material, without increasing line to line capacitance.
To accomplish the above objectives, the present invention provides a method for forming a dual damascene structure in a carbon-based, low-K material. The process begins by providing a semiconductor structure having a first metal pattern thereover, wherein the first metal pattern has a first barrier layer thereon. An organic dielectric layer is formed on the first barrier layer, and a hard mask layer is formed on the dielectric layer. The hard mask layer and the dielectric layer are patterned to form a trench. A second barrier layer is formed over the hard mask layer and on the bottom and sidewalls of the trench. A barc layer is formed over the second barrier layer, thereby filling the trench. The barc layer, the second barrier layer, and the dielectric layer are patterned to form a via opening. The barc layer is removed without faceting the edges of the via opening due to the second barrier layer. The first barrier layer and the second barrier layer are removed. A third barrier layer is formed on the bottom and sidewalls of the trench, on the sidewalls of the via opening, and on the first metal pattern through the via opening. The trench and the via opening are filled with metal to form a damascene structure. The main steps of the present invention are summrized in table 1.
TABLE 1
FIG.
Process Step
4
etch trench 35 in low-K dielectric layer 30 using an
etch chemistry of N
2
, O
2
, H
2
or
with additives like CH
2
F
2
or CH
4
5A
form second barrier layer 36 in trench 35
5A
form BARC layer 40 on second barrier layer 36
5B
form etch mask for via opening 45 etch
6A
etch via opening 45 in BARC layer 40 using N
2
/H
2
reactive ion etch to form via 45
6A
etch via opening 45 in second barrier layer 36 using
CF4/Ar/O2 reactive ion etch
6A
etch via opening 45 in low-K dielectric layer 30 using
a reactive ion etch with N2/O2/H2 or other additives,
stopping on first barrier layer 24 and using second
barrier layer 36 to protect low-K edge,
the photoresist etch mask 42 and the barc layer 40
are also removed by this etch process
6B
remove second barrier layer 36 on bottom of trench
35 and first brrier layer on bottom of via opening
45 using CF
4
/Ar/O
2
reactive ion etch
7
form third barrier layer 50
7
form metal plug
The present invention provides considerable improvement over the prior art. Most importantly, the present invention provides a method for forming a dual damascene structure in an organic, low-K dielectric layer without inducing line

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