Dual damascene process

Details Dual damascene process Dual damascene process

2002-08-27

2004-11-16

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S669000, C438S720000, C438S737000

Reexamination Certificate

active

06818547

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor process, and more particularly to a method for manufacturing interconnects using a dual damascene process.
2. Description of the Related Art
In the fabrication of very large scale integrated (VLSI) circuits, semiconductor devices are generally linked by several metallic interconnecting layers commonly referred to as multilevel interconnects. As the level of circuit integration continues to increase, manufacturing processes are complicated and product yield and reliability is harder to maintain. Dual damascene process is a convenient method for forming multilevel interconnects. Principally, the process includes etching a dielectric layer to form trenches and via holes, and then depositing metal into the trenches and via holes to form the interconnects. The dual damascene process is capable of producing highly reliable interconnects with a relatively high product yield. Due to its versatility, the dual damascene process has become a predominant method for fabricating interconnects.
FIGS.
1
A~
1
F illustrate a conventional process flow to fabricate dual damascene structures to connect semiconductor devices as support contacts. As shown in
FIG. 1A
, semiconductor devices are formed on a semiconductor substrate
100
and composed of gate
102
, source/drain regions
106
and
108
. Semiconductor devices are isolated by isolation structures
104
. A nitride layer
110
is deposited over the gate
102
and a boro-phosphosilicate glass (BPSG) layer
112
is formed over the surface of the semiconductor substrate
100
for insulating. A dielectric layer, tetra-ethyl-ortho-silicate (TEOS),
114
is formed over the BPSG layer
112
.
The dielectric layer
114
is defined by photolithography and etched to form a plurality of trenches
114
a
. First photoresist layer
116
is formed over the dielectric layer
114
to fill the trenches
114
a
. Second photoresist layer
118
is formed over the first photoresist layer as an image layer as shown in FIG.
1
B and the thickness of the second photoresist layer
118
is smaller than the first photoresist layer
116
. The bi-layer photoresist structure can achieve good photolithography quality by thoroughly filling the trenches
114
a.
In
FIG. 1C
, the second photoresist layer
118
is patterned to defined via openings
118
a
above the trenches
114
a
by photolithography. The first photoresist layer
116
is patterned subsequently by dry etching using the patterned second photoresist layer
118
as a mask and via openings
116
a
are formed in the first photoresist layer
116
as
FIG. 1D
shows. In
FIG. 1E
, via openings
102
a
,
106
a
and
108
a
are formed above the gate
102
and the source/drain regions
106
and
108
respectively by etching the boro-phosphosilicate glass (BPSG) layer
112
and the tetra-ethyl-ortho-silicate (TEOS)
114
with the first and second patterned photoresist layers
116
and
118
as mask.
After removing the first and second photoresist layers
116
and
118
, dual damascene openings are formed above the gate
102
and the source/drain regions
106
and
108
. Interconnect structures
120
are formed by filling the dual damascene openings with conductive materials as shown in FIG.
1
F.
Conventionally, the second photoresist layer
118
is Si-containing photoresist material which easily outgasses and contaminates equipment during photolithography. Additionally, dry etching the first photoresist layer
116
with oxygen gas will also oxidize the surface of the second photoresist layer
118
to form silicon oxide. After the first and second photoresist layers
116
and
118
are removed, there will be undesired silicon oxide residue on the semiconductor substrate, creating extra cleaning steps. It will enlarge dielectric oxide via opening critical dimension (CD) while removing the silicon oxide residue.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a dual damascene process with W/TiN as the filling material to prevent residue.
To achieve the above-mentioned object, the present invention provides a dual damascene process including the following steps. A dielectric layer is formed over the surface of a semiconductor substrate which comprises conductive layers or MOS devices. The dielectric layer is patterned to form a plurality of trench openings and a conducting layer is deposited over the dielectric layer to fill the plurality of trenches. A photoresist layer is formed over the conducting layer and defined to form a plurality of via hole patterns above the plurality of trenches. The conducting layer and the dielectric layer are etched using the patterned photoresist layer as a mask to form a plurality of via holes exposing the underlying conductive layers or MOS devices and a dual damascene structure opening is formed.
According to the present invention, the preferred dielectric layer is tetra-ethyl-ortho-silicate (TEOS) or non-doped silicon glass (NSG) and the preferred conducting layer is tungsten (w) or polysilicon. The via plugs in the dual damascene structure can be contacts connecting the MOS devices in the semiconductor substrate and the upper interconnect metal lines.
The dual damascene process can further comprise a step of forming a barrier layer in the via and trench openings before filling the conducting layer. The preferred barrier layer is TiN, TaN or TiW and the preferred thickness is about 250~300 angstroms (Å).
According to one preferred embodiment of the invention, depositing a conducting layer over the barrier layer to fill the plurality of trenches further comprises the steps of: depositing the conducting layer over the barrier layer to fill the plurality of trenches, and etching back the conducting layer to form a smooth surface with a predetermined thickness above the dielectric layer. Etching back the conducting layer can be performed by chemical mechanical polishing (CMP) to form a conducting layer with a thickness between 400 to 500 angstroms.
According to one preferred embodiment of the invention, etching the conducting layer and the dielectric layer with the patterned photoresist layer as a mask to form a plurality of via holes further comprises the steps of: dry etching the conducting layer with the patterned photoresist layer as a mask, removing the photoresist layer, and dry etching the dielectric layer with the conducting layer as a mask to expose the underlying conductive layers or MOS devices and plurality of via holes are formed.


REFERENCES:
patent: 5614765 (1997-03-01), Avanzino et al.
patent: 6211061 (2001-04-01), Chen et al.
patent: 6300235 (2001-10-01), Feldner et al.
patent: 2003/0008490 (2003-01-01), Xing et al

Affiliated with

Also associated with

Rating

Dual damascene process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual damascene process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual damascene process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3340056