Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-08
2004-11-30
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S218000, C257S506000
Reexamination Certificate
active
06825074
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a MOSFET which is formed in a silicon on insulator (SOI) substrate, and more particularly to a method of implanting ions into a silicon layer of the SOI substrate to control a threshold voltage of the SOI-MOSFET. And, the present invention relates to a semiconductor device which is formed in the SOI substrate, and more particularly to a peak ion concentration of the silicon layer of the SOI-MOSFET.
2. Description of the Related Art
A conventional method of manufacturing a semiconductor device will be described below with reference to the cross-sectional views of FIGS.
19
(
a
) through
19
(
f
) and FIGS.
20
(
a
) through
20
(
c
).
At first, an SOI substrate
501
is prepared having a silicon substrate
500
, an oxide film
502
and an SOI layer
504
, as shown in FIG.
19
(
a
). A pad oxide film
506
is formed on the SOI layer
504
, as shown in FIG.
19
(
b
), and then a nitride film (Si
3
N
4
)
508
is formed on the pad oxide film
506
, as shown in FIG.
19
(
c
).
Then, an isolation film
503
is formed by a local oxidation (LOCOS) method or a shallow trench isolation (STI) method, as shown in FIG.
19
(
d
). Thereafter, the pad oxide film
506
is removed, as shown in FIG.
19
(
e
), and then a thin oxide film
510
is formed on the SOI layer
504
, as shown in FIG.
19
(
f
). A thickness of the thin oxide film
510
may be less than 10 nm.
Then, impurity ions
512
are implanted into the SOI layer
504
, as shown in FIG.
20
(
a
). In the n-type SOI-MOSFET, a p-type impurity ion is implanted, and in the p-type SOI-MOSFET, an n-type impurity ion is implanted. Then, a gate electrode
514
is formed on the thin oxide film, as shown in FIG.
20
(
b
). The gate electrode
514
is composed of a poly-silicon, for example. Finally, lightly doped drain (LDD) regions which includes source and drain regions
516
are formed with the use of side walls
518
, as shown in FIG.
20
(
c
).
FIG. 21
is a graph for illustrating the relationship between a gate length and a threshold voltage of the conventional SOI-MOSFET. As the gate length of the SOI-MOSFET is reduced from 0.5 &mgr;m, the threshold voltage of the device gradually falls. However, as the gate length is reduced even further, the fall in the threshold voltage becomes more pronounced, until eventually small reductions in gate length result in large drops in the threshold voltage. This is known as a “short channel effect”. As such when the gate length of the SOI-MOSFET is designed to be about 0.35 &mgr;m, the threshold voltage does not vary to any great extent as a result of manufacturing variation in the gate length. However, when the gate length is designed to be less than 0.15 &mgr;m, the threshold voltage can exhibit wide variation even with only small variation in the manufactured gate length.
FIG. 22
is a graph for illustrating the relationship between a gate length and a sub-threshold coefficient of the conventional SOI-MOSFET. As the gate length of the SOI-MOSFET is reduced from 0.5 &mgr;m, the sub-threshold coefficient S (mV/dec.) gradually rises. However, as the gate length is reduced even further, the rise in the sub-threshold coefficient S becomes more pronounced, until eventually small reductions in gate length result in large increases in the sub-threshold coefficient S. Also, the larger the sub-threshold coefficient S, the larger becomes an off-leak current. As such, small reductions in gate length can result in large increases in the sub-threshold coefficient S and in the off-leak current.
FIGS.
23
(
a
) and
23
(
b
) are graphs for illustrating relationships between a thickness of the SOI layer and a threshold voltage of the conventional SOI-MOSFET when the SOI-MOSFET has two kinds of gate length. It is known a relatively thin SOI layer to help mitigate the short channel effect. However, if the SOI layer is too thin, the threshold voltage suddenly falls off, as shown in FIGS.
23
(
a
) and
23
(
b
).
The conventional SOI-MOSFET is disclosed in an article of Proceeding 1995 IEEE International SOI Conference, October 1995, pp. 116-117, “Characteristics of Submicrometer LOCOS Isolation”, published on October, 1995.
SUMMARY OF THE INVENTION
It is an objective of the invention to provide a method of manufacturing a semiconductor device and a semiconductor device so as to effectively inhibit the short channel effect resulting from a reduction of the gate length attendant with miniaturization of the SOI-MOSFET.
To achieve this object, in a method of manufacturing a semiconductor device and a semiconductor device, impurity ions are implanted into the SOI layer so that a distribution of an impurity ion concentration in the SOI layer inhibits a reduction in a threshold voltage (Vth-rolloff) of the device.
According to the present invention, a reduction in a potential barrier can be effectively inhibited, which in turn can effectively inhibit the short channel effect resulting from a reduction in the gate length.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and accompanying drawings.
REFERENCES:
patent: 6495898 (2002-12-01), Iwamatsu et al.
Jeffrey W. Thomas et al., “Characteristics of Submicrometer LOCOS Isolation”, 1995 IEEE International SOI Conference, Oct. 1995, pp. 116-117.
Le Dung A.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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