Dual damascene patterning method

Details Dual damascene patterning method Dual damascene patterning method

2006-04-10

2009-11-03

Nguyen, Ha Tran T (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S623000, C438S672000, C438S675000, C257SE21579

Reexamination Certificate

active

07611986

ABSTRACT:
A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.

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