Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-10-30
2001-01-09
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S783000, C438S618000, C438S634000, C438S637000
Reexamination Certificate
active
06171951
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a dual damascene. More particularly, the present invention relates to a method of manufacturing a dual damascene by using low dielectric constant (K) material.
2. Background
FIGS. 1A through 1E
are cross-sectional views showing the progression of conventional manufacturing steps in producing a dual damascene.
As shown in
FIG. 1A
, a substrate structure
100
is provided. For clarity, devices within the substrate structure
100
are not sketched. A defined conductive layer
102
is formed in the substrate structure
100
. An oxide layer
104
and a silicon nitride layer
106
aresubsequently formed over the substrate
100
and the conductive layer
102
.
As shown in
FIG. 1B
, the silicon nitride layer
106
is defined by a photolithography method to form an opening exposing the oxide layer
104
. Then, an insulation layer
108
is formed over the defined silicon nitride layer
106
a
and the oxide layer
104
exposed within the opening.
As shown in
FIG. 1C
, a photoresist pattern (not shown) is used to define the insulation layer
108
by, for example, an anisotropic dry etching method. Using the silicon nitride layer
106
a
as an etching mask, the oxide layer
104
within the opening is etched away until the conductive layer
102
and the silicon nitride layer
106
a
are exposed so that trenches
110
a
and
110
b
are formed. Trench
110
a
is formed in the insulation layer
108
(FIG.
1
B), silicon nitride layer
106
a
and oxide layer
104
, and exposes the conductive layer
102
. Trench
110
b
is formed in the insulation layer
108
and exposes the silicon nitride layer
106
a.
The remaining portions of insulation layer
108
are referred to as
108
a,
108
b
and
108
c.
As shown in
FIG. 1D
, a barrier layer
112
is formed over the surface of the trenches
110
a
and
110
b.
A metal layer
114
is then formed over the barrier layer
112
and fills the trenches
110
a
and
110
b.
As shown in
FIG. 1E
, using a chemical mechanical polishing (CMP) method, the redundant portions of metal layer
114
and barrier layer
112
above the insulation layers
108
a,
108
b
and
108
c
are removed to form via
114
a
and conductive lines
114
b
and
114
c.
As the size of semiconductor devices is reduced to 0.25 &mgr;m, the distance between the conductive line
114
b
and the conductive line
114
c
is reduced. Therefore, a capacitor effect will take place on the insulation layer
108
b
located between the conductive lines
114
b
and
114
c.
An additional current is caused by the capacitor effect, hence interfering with the normal operations of the conductive lines
114
b
and
114
c.
RC delay and the reduction of the performance of the devices are also caused by the capacitor effect.
Moreover, the decreasing step coverage of the barrier layer
112
accompanies the reduction in width of the trench
110
a.
Therefore, protruding shapes are formed on the barrier layer
112
at the corners of the trenches
110
a
and
110
b.
These protruding shapes obstruct the deposition of the metal layer
114
.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide an improved dual damascene process for forming dual damascene structure. The dual damascene process is capable of preventing defects, such as the capacitor effect, produced by a conventional dual damascene process.
To achieve these and other advantages and in accordance with the purpose of the invention, a manufacturing method of dual damascene is provided.
The process of the invention comprises the following steps: forming a first dielectric layer over the substrate; forming a hard material layer having a first opening over the first dielectric layer, such that the first opening exposes the first dielectric layer and corresponds to the first conductive layer; forming a second dielectric layer over the hard material layer and covering the exposed first dielectric layer within the first opening; performing a first ion implanting step on the second dielectric layer to densify the second dielectric layer; forming a hard mask layer having a second opening over the second dielectric layer, wherein the second opening is formed corresponding to the first dielectric layer, and the second opening is broad at the top and narrow at the bottom; using the hard mask layer and the hard material layer as etching stop layers to define the second dielectric layer and the first dielectric layer to connect the first opening and the second opening to form a third opening, wherein the third opening exposes the first conductive layer; performing at least a second ion implanting step on the exposed second dielectric layer to densify the second dielectric layer; forming a barrier layer in the third opening; and forming a second conductive layer to fill the third opening, such that the second conductive layer and the second dielectric layer have the same height.
The present invention utilizes a low dielectric constant material to form the dielectric layers and to prevent current due to the reduced line width. An implanting step is then performed on the dielectric layers to reduce the incoherence and fragility of the dielectric layers and to protect the dielectric layers from damage in the subsequent processes.
The present invention utilizes the hard mask layer formed over the dielectric layer to reduce the difficulty of the barrier layer depositing process. The openings formed within the hard mask layer are broad at the top and narrow at the bottom, so that the barrier layer is more easily deposited into the opening and the subsequent deposition step of the conductive material layer is easily performed. Moreover, the hard mask layer can be utilized as the etching stop layer in the CMP process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5496776 (1996-03-01), Chien et al.
patent: 5674784 (1997-10-01), Jang et al.
patent: 5730835 (1998-03-01), Roberts et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5888902 (1999-03-01), Jun
patent: 5904566 (1999-05-01), Tao et al.
patent: 5972789 (1999-10-01), Jeng et al.
patent: 6037664 (2000-03-01), Zhao et al.
Lee Tzung-Han
Lu Tse-Yi
Davis Jamie L.
Jr. Carl Whitehead
United Microelectronic Corp.
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