Dual damascene metallization

Details Dual damascene metallization Dual damascene metallization

1999-08-24

2001-03-27

Beck, Shrive (Department: 1762)

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

C427S096400, C427S123000, C438S628000, C438S629000, C438S643000, C438S644000, C438S648000

Reexamination Certificate

active

06207222

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a metallization method for manufacturing semiconductor devices. More particularly, the present invention relates to metallization of dual damascene via and wire definitions in a dielectric layer to form metal interconnects and metal via plugs.
2. Background of the Related Art
Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (VLSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines or other features. Reliable formation of these interconnect features is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, must decrease resulting in larger aspect ratios for the features. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free features having high aspect ratios wherein the ratio of feature width to feature height is 4:1 or larger. One such method involves selective chemical vapor deposition (CVD) of material only on exposed nucleation surfaces as provided on the substrate surface. Selective CVD involves the deposition of a film layer upon contact of a component of the chemical vapor with a conductive substrate. The component nucleates on such substrate creating a metal surface on which further deposition proceeds.
Selective CVD metal deposition is based on the fact that the decomposition of a CVD metal precursor gas usually requires a source of electrons from a conductive nucleation film. In accordance with a conventional selective CVD metal deposition process, the metal should grow in the bottom of an aperture where either a metal film or doped silicon or metal silicide from the underlying conductive layer has been exposed, but should not grow on dielectric surfaces such as the field and aperture walls. The underlying metal films or doped silicon are electrically conductive, unlike the dielectric field and aperture walls, and supply the electrons needed for decomposition of the metal precursor gas and the resulting deposition of the metal. The result obtained through selective deposition is an epitaxial “bottom-up” growth of CVD metal in the apertures capable of filling very small dimension (<0.25 &mgr;m), high aspect ratio (>5:1) via or contact openings.
Elemental aluminum (Al) and its alloys have been the traditional metals used to form lines and plugs in semiconductor processing because of aluminum's low resistivity, superior adhesion to silicon dioxide (SiO
2
), ease of patterning, and high purity. Furthermore, aluminum precursor gases are available which facilitate the selective CVD process described above. However, aluminum has higher resistivity and problems with electromigration. Electromigration is a phenomenon that occurs in a metal circuit while the circuit is in operation, as opposed to a failure occurring during fabrication. Electromigration is caused by the diffusion of the metal in the electric field set up in the circuit. The metal gets transported from one end to the other after hours of operation and eventually separates completely, causing an opening in the circuit. This problem is sometimes overcome by Cu doping and texture improvement. However, electromigration is a problem that gets worse as the current density increases.
Copper and its alloys, on the other hand, have even lower resistivities than aluminum and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increase device speed. However, the primary problems with integrating copper metal into multilevel metallization systems are (1) the difficulty of patterning the metal using etching techniques, and (2) the difficulty in filling small vias using PVD given the lack of mature CVD processes. For devices of submicron minimum feature size, wet etch techniques for copper patterning have not been acceptable due to liquid surface tension, isotropic etch profile, and difficulty in over-etch control and a reliable dry etch process is not available.
Several methods have been proposed for producing patterned copper interconnects, including selective electroless plating, selective chemical vapor deposition, high temperature reactive ion etching and lift off processing. Electroless plating requires that the floor of an interconnect be seeded to make the floor conductive. The conductive floor can then be charged to attract copper from a solution or bath.
Selective chemical vapor deposition typically involves the decomposition of a metal precursor gas on an electrically conducting surface. However, a reliable and mature process for selective CVD copper is not available.
High temperature reactive ion etching (RIE), or sputter etching, has also been used to pattern a copper layer. Furthermore, the RIE can be used in conjunction with lift off processing in which excess metal is lifted off the structure by a release layer to leave a planar surface having a copper feature formed therein.
Yet another technique for metal wiring of copper comprises the patterning and etching of a trench and/or contact within a thick layer of insulating material, such as SiO
2
. Thereafter, a thin layer of a barrier metal, such as Ti, TiW or TiN, may be provided on top of the insulating layer and within the trench and/or contact to act as a diffusion barrier to prevent inter-diffusion of the metal to be subsequently deposited into the silicon, and between such metal and oxide. After barrier metal deposition, a layer of copper is deposited to completely fill the trench.
A known metallization technique provides a method for forming a dual damascene interconnect in a dielectric layer having dual damascene via and wire definitions, wherein the via has a floor exposing an underlying layer. The method includes physical vapor deposition of a barrier layer, physical vapor deposition of a conductive metal, preferably copper, and then electroplating of the conductive metal to fill the vias and trenches. Finally, the deposited layers and the dielectric layers are planarized, such as by chemical mechanical polishing, to define a conductive wire.
Referring to
FIGS. 1A through 1E
, a cross-sectional diagram of a layered structure
10
is shown including a dielectric layer
16
formed over an underlying layer
14
which contains electrically conducting features
15
. The underlying layer
14
may take the form of a doped silicon substrate or it may be a first or subsequent conducting layer formed on a substrate. The dielectric layer
16
is formed over the underlying layer
14
in accordance with procedures known in the art to form a part of the overall integrated circuit. Once deposited, the dielectric layer
16
is etched to form a dual damascene via and wire definition, wherein the via has a floor
30
exposing a small portion of the conducting feature
15
. Etching of the dielectric layer
16
is accomplished with any dielectric etching process, including plasma etching. Specific techniques for etching silicon dioxide and organic materials may include such compounds as buffered hydrofluoric acid and acetone or EKC, respectively. However, patterning may be accomplished using any method known in the art.
Referring to
FIG. 1A
, a cross-sectional diagram of a dual damascene via and wire definition formed in the dielectric layer
16
is shown. The via and wire definition facilitates the deposition of a conductive interconnect that will provide an electrical connection with the underlying conductive feature
15
. The definition provides vias
32
having via walls
34
and a floor
30
exposing at least a portion of the conductive feature
15
, and trenches
17
having tren

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