Dual damascene interconnection with metal-insulator-metal...

Details Dual damascene interconnection with metal-insulator-metal... Dual damascene interconnection with metal-insulator-metal...

2007-08-30

2008-07-15

Sarkar, Asok K (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S253000, C438S597000, C257SE21579

Reexamination Certificate

active

07399700

ABSTRACT:
Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.

REFERENCES:
patent: 6483142 (2002-11-01), Hsue et al.
patent: 6512260 (2003-01-01), Hsue et al.
patent: 6740974 (2004-05-01), Yoshitomi
patent: 6746914 (2004-06-01), Kai et al.
patent: 6750115 (2004-06-01), Ning et al.
patent: 2003/0012117 (2003-01-01), Ogawa et al.
patent: 2002-0018610 (2002-03-01), None

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