Dual damascene interconnect structure using low stress...

Details Dual damascene interconnect structure using low stress... Dual damascene interconnect structure using low stress...

2006-04-25

2006-04-25

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C438S624000, C438S637000, C438S666000

Reexamination Certificate

active

07034400

ABSTRACT:
A metallization insulating structure, havinga substrate;a substantially fluorine free insulating layer formed on the substrate, having a height, hi;a fluorine containing insulating layer formed on the substantially fluorine free insulating layer, having a height hf.

REFERENCES:
patent: 3620833 (1971-11-01), Gleim et al.
patent: 4300989 (1981-11-01), Chang
patent: 5011732 (1991-04-01), Takeuchi et al.
patent: 5181985 (1993-01-01), Lampert et al.
patent: 5219791 (1993-06-01), Freiberger
patent: 5306671 (1994-04-01), Ogawa et al.
patent: 5378317 (1995-01-01), Kashiwase et al.
patent: 5380397 (1995-01-01), Fukuyama et al.
patent: 5384281 (1995-01-01), Kenney et al.
patent: 5397748 (1995-03-01), Watanabe et al.
patent: 5423945 (1995-06-01), Marks et al.
patent: 5429995 (1995-07-01), Nishiyama et al.
patent: 5451543 (1995-09-01), Woo et al.
patent: 5466638 (1995-11-01), Eguchi
patent: 5497545 (1996-03-01), Watanabe et al.
patent: 5527718 (1996-06-01), Seita et al.
patent: 5644166 (1997-07-01), Honeycutt et al.
patent: 5661334 (1997-08-01), Akram
patent: 5753564 (1998-05-01), Fukada
patent: 5821175 (1998-10-01), Engelsberg
patent: 5930655 (1999-07-01), Cooney, III et al.
patent: 5976972 (1999-11-01), Inohara et al.
patent: 6004883 (1999-12-01), Yu et al.
patent: 6040243 (2000-03-01), Li et al.
patent: 6066577 (2000-05-01), Cooney, III et al.
patent: 6214730 (2001-04-01), Cooney, III et al.
patent: 6307265 (2001-10-01), Anand et al.
patent: 6310300 (2001-10-01), Cooney, III et al.
patent: 6326301 (2001-12-01), Venkatesan et al.
patent: 6333257 (2001-12-01), Aoi
patent: 6420261 (2002-07-01), Kudo
patent: 07094606 (1995-07-01), None
patent: 94-12488 (1999-06-01), None
S. M. Sze, VLSI Technology, second edition, p233-234,266-267, 1988.
1990 Proceedings, Seventh International IEEE VLSI Multilevel Interconnection Conference, C.M. Dalton, p. 289-95, Jan. 1990.

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