Dual damascene integration scheme for preventing copper...

Details Dual damascene integration scheme for preventing copper... Dual damascene integration scheme for preventing copper...

2005-09-06

2005-09-06

Lee, Hsien-Ming (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S627000, C438S629000, C438S633000, C438S637000, C438S687000, C438S713000

Reexamination Certificate

active

06939793

ABSTRACT:
A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.

REFERENCES:
patent: 6083822 (2000-07-01), Lee
patent: 6136682 (2000-10-01), Hegde et al.
patent: 6150723 (2000-11-01), Harper et al.
patent: 6465889 (2002-10-01), Subramanian et al.
patent: 6576982 (2003-06-01), You et al.
patent: 6577009 (2003-06-01), You et al.
patent: 6663787 (2003-12-01), You et al.
patent: 6677679 (2004-01-01), You et al.

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