Dual-damascene bit line structures for microelectronic...

Details Dual-damascene bit line structures for microelectronic... Dual-damascene bit line structures for microelectronic...

2002-08-21

2004-02-24

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S622000, C438S637000, C438S639000

Reexamination Certificate

active

06696339

ABSTRACT:

TECHNICAL FIELD
The present invention is directed to fabricating conductive structures, such as bit lines and interlayer contacts, in the manufacturing of microelectronic devices.
BACKGROUND
Manufacturers of microelectronic devices are continually reducing the size and increasing the density of components in integrated circuits to (a) increase the speed and capacity of devices and (b) reduce the power consumption. For example, to increase the capacity of a memory device, it is desirable to reduce the size of memory cells without impairing performance. Memory device manufacturers accordingly seek to reduce the size and/or increase the density of components in memory cells.
Memory cells include integrated circuitry comprised of several different submicron components, such as active areas, bit lines, wordlines, bit line contacts and cell plugs. The bit lines, wordlines and other components are electrically coupled to appropriate contact areas by the bit line contacts and cell plugs. As integrated circuits are scaled down, it becomes more difficult to fabricate the individual components. The increasing difficulty of fabricating small components increases the cost of fabricating integrated circuits. For example, as memory cells shrink, several micro-fabrication processes require extensive development to form such small structures with the necessary precision and repeatability for production level processing. The equipment and procedures for producing ever smaller components accordingly becomes more expensive.
One process that may become a limiting factor for producing small components in high-performance devices is photolithography. Photolithographic processes dramatically increase the cost of manufacturing a given device because they are time-consuming and require very expensive equipment. For example, a conventional bit line structure requires several photolithographic procedures to form the bit lines, the bit line contacts between the bit lines and the active areas, and the cell plugs that are electrically connected to other portions of the active areas. To better understand the problems with conventional techniques for fabricating bit lines in memory cells,
FIGS. 1-8B
illustrate a conventional process for fabricating raised bit lines.
FIG. 1
is a top plan view illustrating a portion of a memory cell array
10
. The memory cell array
10
includes a dielectric layer
20
, a plurality of bit line openings
22
extending through the dielectric layer
20
, and a plurality of cell plug openings
24
extending through other portions of the dielectric layer.
FIGS. 2A
,
3
A,
4
A,
5
A,
6
A,
7
A and
8
A are all schematic cross-sectional views taken along line A—A of
FIG. 1
at various stages of forming a bit line structure using conventional processing techniques.
FIGS. 2B
,
3
B,
4
B,
5
B,
6
B,
7
B and
8
B are schematic cross-sectional views taken along B—B of
FIG. 1
at corresponding stages of fabricating a bit line structure in a memory cell in accordance with conventional techniques.
Referring to
FIGS. 2A and 2B
, the memory cell
10
includes a substrate
12
having a plurality of shallow trench isolation (STI) structures
14
and active areas
16
(identified by reference numbers
16
a
and
16
b
) between the STI structures
14
. In
FIG. 2A
, the STI structures
14
separate bit line active areas
16
a
, and in
FIG. 2B
, the STI structures
14
separate cell active areas
16
b
.
FIGS. 2A and 2B
illustrate the memory cell
10
after a conductive material
30
has been deposited into the bit line openings
22
and the cell plug openings
24
. The conductive layer
30
is planarized to form bit line contacts
32
in the bit line openings
22
and cell plugs
34
in the cell plug openings
24
. An oxide layer
40
is then deposited over the workpiece.
FIGS. 3A-5B
are schematic cross-sectional views of subsequent stages in the conventional method that illustrate constructing bit lines for the memory cell
10
. Referring to
FIGS. 3A and 3B
, the oxide layer is patterned using a first photolithographic process and then openings
42
are etched in the oxide layer
40
over only the bit line contacts
32
. The oxide layer
40
is not removed over the cell plugs
34
. Referring to
FIGS. 4A and 4B
, a first conductive layer
50
is deposited on the workpiece and then a second conductive layer
60
is deposited on the first conductive layer
50
. The first conductive layer
50
can be polysilicon or another conductive material, and the second conductive material
60
can be tungsten, tungsten suicide or other suitable materials. The first and second conductive layers
50
and
60
are patterned using a second photolithographic process to form raised bit lines. For example,
FIGS. 5A and 5B
illustrate the memory cell
10
after performing the second photolithographic process and etching the first and second conductive layers
50
and
60
to form a plurality of raised bit lines
65
. The bit lines
65
are raised relative to the top surface of the bit line contacts
32
because the first conductive layer
50
covers the upper surface of the bit line contacts
32
. After forming the bit lines
65
, the conventional techniques proceed with protecting the bit lines
65
and forming contacts to the cell plugs
34
.
FIGS. 6A-8B
illustrate subsequent stages of the conventional techniques in which contacts to the cell plugs
34
are constructed after forming the raised bit lines
65
. Referring to
FIGS. 6A and 6B
, a second dielectric layer
70
is deposited over the memory cell
10
to protect the bit lines
65
. Referring to
FIGS. 7A and 7B
, the dielectric layer
70
is patterned using a third photolithographic process and then etched to form contact holes
72
in the dielectric layer
70
. The contact holes
72
are formed only over the cell plugs
34
. The contact holes
72
are accordingly formed in a separate photolithographic procedure in addition to the photolithographic procedures for forming the bit line contacts
32
and the bit lines
65
. After forming the contact holes
72
, a layer of conductive material is deposited over the memory cell
10
to fill the contact holes
72
.
FIGS. 8A and 8B
illustrate the memory cell
10
after a conductive layer
80
has been deposited to fill the contact holes
72
and then planarized to form individual contacts
82
that are electrically coupled with the cell plugs
34
.
One concern regarding conventional techniques is that a large number of photolithographic procedures are necessary to form bit lines, contacts and cell plugs. For example, to form the structure shown in
FIGS. 5A and 5B
from the structure shown in
FIGS. 4A and 4B
, a layer of resist is deposited over the second conductive layers
60
, the resist layer is then patterned using costly stepper tools, and then the first and second conductive layers
50
and
60
are etched to form the bit lines
65
. The formation of the contacts
82
shown in
FIG. 8B
requires a separate, additional photolithographic procedure. For example, to form the structure shown in
FIGS. 7A and 7B
from the structure shown in
FIGS. 6A and 6B
, another layer of resist is deposited onto the dielectric layer
70
, the dielectric layer
70
is then patterned using photolithographic techniques, and the contact holes
72
are then etched through the dielectric layer. The additional photolithographic process for forming the contacts
82
increases the cost of manufacturing the memory cell
10
because of the equipment, time and materials that are necessary for the additional photolithographic procedures.
Another concern regarding conventional processing techniques is that photolithographic procedures can induce errors and be a limiting factor in manufacturing small components in high densities. It will be appreciated that the tolerances significantly decrease for forming small, high-density components because the spacing between the components significantly decreases. As a result, the photolithographic procedures must be more precise to properly align the bit lines
65
with the bit

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