Dual-counterdoped channel field effect transistor and method

Details Dual-counterdoped channel field effect transistor and method Dual-counterdoped channel field effect transistor and method

2005-11-01

2005-11-01

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S289000

Reexamination Certificate

active

06960499

ABSTRACT:
A field effect transistor with a dual-counterdoped channel is disclosed. The transistor features a channel comprising a first doped region (28) and a second doped region (26) underlying the first doped region. A source and drain (32) are formed adjacent to the channel. In one embodiment of the present invention, the first doped region (28) is doped with arsenic, while the second doped region (26) is doped with phosphorus. The high charge-carrier mobility of the subsurface channel layer (28) allowing a lower channel dopant concentration to be used, which in turn allows lower source/drain pocket doping. This reduces the capacitance and response time of the transistor.

REFERENCES:
patent: 5548143 (1996-08-01), Lee
patent: 5586073 (1996-12-01), Hiura et al.
patent: 5786620 (1998-07-01), Richards et al.
patent: 5923987 (1999-07-01), Burr
patent: 6117691 (2000-09-01), Hsu et al.
patent: 6121666 (2000-09-01), Burr

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