Dual-chip integrated circuit package with a chip-die pad...

Details Dual-chip integrated circuit package with a chip-die pad... Dual-chip integrated circuit package with a chip-die pad...

1999-12-28

2001-10-23

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S666000, C257S777000, C257S724000

Reexamination Certificate

active

06307257

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a new structure for dual-chip integrated circuit package which is characterized in the use of leads of a leadframe to provide firm support and electrical connection with external devices to the chips.
2. Description of Related Art
Integrated circuit chips are typically packed in packages for easy handling and utilization. To allow increased functionality from a single integrated circuit package, it is usually desired to pack two or more integrated circuit chips rather than just one in the integrated circuit package. An integrated circuit package that packs two integrated circuit chips therein is customarily referred to as a dual-chip integrated circuit package.
The U.S. Pat. No. 5,793,108 discloses a dual-chip integrated circuit package.
FIG. 5
is a schematic sectional diagram showing the structure of this dual-chip integrated circuit package. As shown, this dual-chip integrated circuit package includes a leadframe
200
having a die pad
201
for mounting a first integrated circuit chip
220
and a second integrated circuit chip
240
. The first integrated circuit chip
220
has its front side
221
attached to the die pad
201
by means of an insulative adhesive film
210
. The bonding pads
223
on the first integrated circuit chip
220
are electrically connected via a plurality of gold wires
250
to the first surface
202
a
of the leads
202
of the leadframe
200
. An insulative adhesive layer
230
is then coated on the back side
222
of the first integrated circuit chip
220
for attaching the first integrated circuit chip
220
to the back side
242
of the second integrated circuit chip
240
. The bonding pads
243
on the front side
241
of the second integrated circuit chip
240
are electrically connected via a plurality of gold wires
260
to a second surface
202
b
of the leads
202
. Further, an encapsulant
270
is formed to encapsulate the first integrated circuit chip
220
, the second integrated circuit chip
240
, and the inner part of the leads
202
. Electronic components and electric circuits are formed on the front side
221
of the first integrated circuit chip
220
and the front side
241
of the second integrated circuit chip
240
.
The forgoing dual-chip integrated circuit package, however, has the following drawbacks. First, it requires the bonding pads
223
on the front side
221
of the first integrated circuit chip
220
to be exposed out of the die pad
201
so as to facilitate the connection of the gold wires
250
. This requires the jointed area between the first integrated circuit chip
220
and the die pad
201
to be smaller than the area of the front side
221
of the first integrated circuit chip
220
. However, after the second integrated circuit chip
240
has been attached to the first integrated circuit chip
220
, the beneath of the bonding pads
243
on the second integrated circuit chip
240
is a void space. As a consequence, as shown in
FIG. 6
, during the wire-bonding process to connect the bonding wires
260
, the second integrated circuit chip
240
is only partly supported by the fixture
280
, which would easily cause the areas near the bonding pads
243
on the second integrated circuit chip
240
and the bonding pads
223
on the first integrated circuit chip
220
to be cracked. Second, since the front side
221
of the first integrated circuit chip
220
is attached to the die pad
201
in a direct face-to-face manner, the first integrated circuit chip
220
could be easily subject to delamination during temperature changes in the manufacture process. This is because that the first integrated circuit chip
220
differs in Coefficient of Thermal Expansion (CTE) from the die pad
201
. The direct face-to-face attachment also requires the insulative adhesive film
210
to be large enough to cover the whole of the die pad
201
. This practice, however, would considerably increase the manufacture cost. Moreover, the insulative adhesive film
210
being made large would hamper the drainage of the air between the insulative adhesive film
210
and the die pad
201
and the air between the insulative adhesive film
210
and the first integrated circuit chip
220
, which would undesirably cause voids to be formed therebetween. Under high-temperature condition, the existence of such voids would cause a popcorn effect, which could damage the integrated circuit package structure. Still one drawback is that when the foregoing dual-chip integrated circuit package is formed as a low profile package, the gap between the bottom side of the die pad and the bottom of a cavity of an encapsulation mold (not shown) would become very small, causing the resin flow introduced into the encapsulation mold to be slowed down when passing through the gap, resulting in the undesired thus-forming of voids in the formed encapsulant. The forming of these voids could also lead to the problem of a popcorn effect.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a dual-chip integrated circuit package, which can help prevent delamination from taking place in the interface between the chips and the leadframe.
It is another objective of this invention to provide a dual-chip integrated circuit package, which can provide firm support to the bonding pads on the chips so that the chips can be prevented from being cracked during the wire-bonding process.
It is still another objective of this invention to provide a dual-chip integrated circuit package, which can be more assured in reliability and quality.
In accordance with the foregoing and other objectives, the invention proposes a new structure for dual-chip integrated circuit package. The dual-chip integrated circuit package of the invention includes: (a) a leadframe having a plurality of first leads and a plurality of second leads, with a spacing being defined between the first and second leads; the first leads each having an extending portion; (b) a first integrated circuit chip having a front side and a back side, with the front side being formed with a plurality of bonding pads; the first integrated circuit chip being attached to the extending portions of the first leads in such a manner that the front side thereof is attached to extending portions, allowing the bonding pads on the first integrated circuit chip to be positioned in the spacing; (c) a second integrated circuit chip having a front side and a back side, with the front side being formed with a plurality of bonding pads; the second integrated circuit chip being attached to the first integrated circuit chip in a back-to-back manner; (d) a plurality of first electric connection means for electrically connecting the bonding pads on the first integrated circuit chip to the second leads of the leadframe; (e) a plurality of second electric connection means for electrically connecting the bonding pads on the second integrated circuit chip to at least one of the first leads and the second leads of the leadframe; and (f) an encapsulant for encapsulating the first integrated circuit chip, the second integrated circuit chip, the first and second electric connection means, and an inner part of the first and second leads of the leadframe.
In the foregoing dual-chip integrated circuit package, the electric connection means can be either gold wires or copper wires. The electric connection of the chip with the leads of the leadframe can also be accomplished by TAB (Tape Automated Bonding) techniques.
It is a characteristic feature of the invention that each of the first leads are extended to form an extending portion, preferably being downset from the plane where the leadframe positions. This downset arrangement of the extending portion can help allow the resin flow use in the molding process to be more evenly distributed, thus preventing the forming of voids in the resulted encapsulant. Further, in order to allow planeness to the extending portion of the first leads, they can be

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