Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-06
2001-01-30
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S306000, C438S307000, C438S516000, C438S528000, C438S530000
Reexamination Certificate
active
06180476
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with ultra-shallow source/drain extensions.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source/drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultra-shallow source and drain extensions (less than 30 or 40 nanometer (nm) junction depth). Forming source and drain extensions with junction depths of less than
30
nm is very difficult using conventional fabrication techniques. Conventional ion implantation and diffusion doping techniques make transistors on the IC susceptible to short-channeling effects, which result in a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically into the bulk semiconductor substrate.
Thus, there is a need for a method of manufacturing ultra-shallow source and drain extensions that does not utilize a conventional double implant process. Further still, there is a need for transistors that have ultra-shallow junction source and drain extensions. Even further still, there is a need for an efficient method of manufacturing source and drain extensions that minimizes ion implantation channeling effect and TED effect.
SUMMARY OF THE INVENTION
The present invention relates to a method of manufacturing an integrated circuit. The method includes forming at least a portion of a gate structure on a top surface of a substrate, providing a pre-amorphization implant, doping the substrate for drain and source extension, providing a post-amorphization implant, providing spacers that abut the gate structure, doping the substrate to form source and drain regions, and thermally annealing the substrate. The pre-amorphization implant creates a first amorphous region near the top surface of the substrate, and the post-amorphization implant creates a deep amorphous region in the substrate.
The present invention still further relates to a method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors having shallow source and drain extensions. The method includes steps of forming at least a part of a gate structure on a top surface of a semiconductor substrate, providing a shallow amorphization implant, doping the substrate, providing a deep amorphization implant, providing spacers that abut the gate structure, doping the substrate to form source and drain regions, and thermally annealing the substrate, thereby forming source and drain extensions having a thickness of less than 30 nm. The shallow amorphization implant creates a shallow amorphous region near the top surface, and the deep amorphization implant creates a deep amorphous region in the substrate.
The present invention still further relates to a method of providing a plurality of ultra-shallow drain/source extensions for field effect transistors in an ultra-large scale integrated circuit. The method includes forming a plurality of at least a portion of gate structures on a top surface of a silicon substrate, providing a first amorphization implant, doping the substrate for the drain and source extensions, providing a second amorphization implant, providing spacers that abut the gate structure, doping the substrate to form source and drain regions, and thermally annealing the substrate to form the ultra-shallow drain/source extensions. The first amorphization implant creates a first amorphous semiconductor region near the top surface of the substrate, and the second amorphization implant creates a deep amorphous region in the substrate.
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Advanced Micro Devices , Inc.
Foley & Lardner
Pham Long
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