Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2006-09-19
2006-09-19
Le, Thong Q. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S196000
Reexamination Certificate
active
07110306
ABSTRACT:
A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.
REFERENCES:
patent: 5940329 (1999-08-01), Seitsinger et al.
patent: 5978307 (1999-11-01), Proebsting et al.
patent: 6259634 (2001-07-01), Kengeri et al.
patent: 6418063 (2002-07-01), Seitsinger et al.
patent: 6442078 (2002-08-01), Arimoto
patent: 6877071 (2005-04-01), Sherman
Butler Douglas Blaine
Jones, Jr. Oscar Frederick
Parris Michael C.
Hogan & Hartson LLP
Kubida William J.
Meza Peter J.
United Memories Inc.
LandOfFree
Dual access DRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dual access DRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual access DRAM will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3580576