Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Patent
1997-07-10
1999-02-16
Bowers, Charles
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
438778, 438780, 438788, 438789, 438624, 438760, H01L 2345
Patent
active
058720642
ABSTRACT:
A method of depositing an inter layer dielectric. A first layer using plasma enhanced chemical vapor deposition (CVD) is deposited. It is followed by a second layer, deposited using sub atmospheric CVD. The second layer is argon sputter etched.
REFERENCES:
patent: 3617463 (1971-11-01), Gregor et al.
patent: 4702795 (1987-10-01), Douglas
patent: 4797375 (1989-01-01), Brownell
patent: 4872947 (1989-10-01), Wang et al.
patent: 4952274 (1990-08-01), Abraham
patent: 4983540 (1991-01-01), Yamaguchi et al.
patent: 5270264 (1993-12-01), Andideh et al.
patent: 5514624 (1996-05-01), Morozumi
patent: 5563104 (1996-10-01), Jang et al.
patent: 5679606 (1997-10-01), Wang et al.
patent: 5691573 (1997-11-01), Avanzino et al.
Kotani, H., et al., "Sputter Etching Planarization for Multilevel Metallization", J. Electrochem. Soc.: Solid State Science & Tech. Mar. 1983, pp. 645-648.
Vossen, J., et al., "Back Scattering of Material Emitted from RF-Sputtering Targets", RCA Review, Jun. 1970, pp. 293-305.
Valletta R.M, "Control of Edge Profile In Sputter Etching", IBM Tech. Disc. Bull. vol. 10, No. 12, May 1968, p. 1974.
Huff Brett E.
Moghadam Farhad
Bowers Charles
Intel Corporation
Nguyen Thanh T.
LandOfFree
DSAD process for deposition of inter layer dielectric does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with DSAD process for deposition of inter layer dielectric, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DSAD process for deposition of inter layer dielectric will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2062357